Pick a layer and stick with it

One of the nice things about newer, faster busses like DDR3 and DDR4 is on-die termination.  They are nice because you don’t have a bunch of components clogging up your routing layers, and I would say more importantly, it limits your required layer transitions which can help make your boards quieter.  So take advantage of the fact that you don’t have to route out to a terminator and try to keep your layer transitions limited to underneath the IC.  The area under the IC is a particularly exciting location on the board, and also happens to be the best place for layer transitions.

In a recent aricle in Printed Circuit Design and Fabrication Magazine, I discuss the EMI problems associated with layer transitions.  The article can be found here: http://pcdandf.com/cms/component/content/article/171-current-issue/9656-designers-notebook
Bascially, a stitching via is needed anywhere you transition a signal between layers, to provide a continuous return current path for the signal.  I have discussed return current paths in several previous blogs, but to summarize, broken return path = radiating signal.  This is why a stitching via is needed when a signal transitions between layers.  Well, more precisely, a stitching “thingy” – in the case that the different return paths are planes with the same voltage (usually ground), a via will work.  But if they are at different potentials, a capacitor should be used.  Where on the board are there the most vias and capacitors?  Just around the IC.  This makes it the best place to do any layer transitioning.

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Posted January 7th, 2013, by

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Commented on March 4, 2014 at 5:54 am
By Donald Acker

I have a question about Vert. Ref Plane Signal/Signal errors. If a trace is routed on layer 1 uses a via to get to layer 3 with a ground layer between them on layer 2, why is this an Error? Will not the return current still travel on layer 2 and therefore not be an Error? If this is true how can I make HyperLynx not treat this as an Error? The stackup is a 6 layer board: Top, Gnd, Sig1, Sig2, Pwr & Bottom.

Commented on March 4, 2014 at 5:58 am
By Donald Acker

I made a mistake, this is an 8 layer board: Top, Gnd1, Sig1, Pwr, Gnd2, Sig2, Gnd3 & Bottom.

Commented on September 3, 2014 at 2:09 pm
By Patrick Carrier

Hi Donald–
The issue is that when you transition to Layer 3, you are actually now referencing BOTH Layer 2 and Layer 4. If you check out my blog from 10/10/12 (and the referenced article), I talk about this in more detail. At high frequencies, when the signal is propagating, it has no idea what a plane is connected to. It will couple onto whatever the nearest “hunks” of metal are – planes and traces (which causes crosstalk) – as they represent the lowest-impedance path for the signal. So for your signal on Layer 3, it is now coupling energy onto both Layer 2 and Layer 4, so there must be some connection between Layer 4 and Layer 2 near that signal via to allow for a continuous return path for the percentage of return current which is now on Layer 4. If those planes are at different potentials, a stitching cap must be used. Actually, a number of stitching caps are best to give you a low-impedance path across a range of frequencies. This is why I was advocating “picking a layer and sticking with it”, since you are effectively making any “layer changes” right at the IC where there tend to be a number of caps already.

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