DesignCon 2010 – Next week
You may have noticed on the [SI-LIST] that everyone and their brother have been posting information about DesignCon. Well it is right around the corner with Tutorials kicking the week off on Monday, just 3 days away.
Hopefully you’ve got your bags packed and you’re ready to go! Online registration closed yesterday but you can still get into the conference if you show up in Santa Clara and register at the event.
Here are some highlights of things that will I think will be interesting in the signal integrity and PCB space at the conference that you may want to check out:
- In the area of Tutorials:
- Mentor has several Technical panels we’re hosting:
- There are a ton of great papers that will be presented. Here are just a few:
- Estimation of Simultaneous Switching Noise from the Power Distribution Network Impedance in LPDDR2 Systems
- Impact of Copper Surface Texture on Loss: A model that works
- PWB Manufacturing Variability Effects on High Speed SerDes Links
- Cost Effective Crosstalk Management & Decision Making
- Additional Trace Losses due to Glass-Weave Periodic Loading
- Analysis of FPGA PDN Noise Propagation by die/package 3D Modeling
- Interconnect Considerations for DDR Timing Closure beyond 1600Mbps
Mentor will also have a TecPreview session on Wednesday @ 2:00pm where we’ll talk a bit about modeling for SerDes interfaces called What engineers need to know about SERDES, SPICE, and IBIS-AMI.
Be sure and stop by booth #320 and say “hi” and register for you chance to win that jacket I talked about in my previous blog.
Posted January 29th, 2010, by Steve McKinney
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- An Integrity Cocktail – Mixing SI and PI
- SI and PI – two flavors of Integrity
- Back side cap mounting
- Does trace width matter much?
- How to connect a capacitor?