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24 June, 2015

This is the third post in a three part series that examines the problem of SSN and explores methods of reducing SSN in your designs.

In the first installment of our blog series on Simultaneously Switching Noise, we went through an overview of SSN and explained its relevance to high-speed parallel busses such as DDR4. In the second post, we examined the effects of a poorly designed Power Distribution Network (PDN) on SSN and signal integrity. This final post will elaborate further on the Data Bus Inversion (DBI) option introduced at the conclusion of the previous post.

DBI is an optional feature in DDR4.  If DBI is enabled, then when the driver (controller during a write or DRAM during a read) is sending out data on a lane, it counts the number of “0” (logic low) bits.  If the number of bits driving “0” in the lane is five or more, then the entire byte is inverted, and a ninth bit indicating DBI is asserted low.  This ensures that out of the 8 DQ bits and the 9th DBI bit, at least five bits are “1” during any given transaction.  This also ensures that out of the entire data lane, the maximum total number of signals transitioning is either five 1’s to 9 1’s or vice-versa.  There can never be a situation where all bits go from 0 to 1 or from 1 to 0.

So, if we run the same data bus with data patterns which would be the output of the DBI logic, we get the waveform for DQ0 in Figure 1.

Figure 1: DBI processed bit patterns with improved PDN

Figure 1: DBI processed bit patterns with improved PDN

The eye-height for DQ0 in this case is over 315mV, which surpasses all the other conditions.  Now, since DBI is data dependent, the benefits of DBI may vary and need to be analyzed before implementation.

Thank you for following our blog series on SSN—we hope you find this information valuable and share your thoughts in the comments. With a good design of the PDN, and possibly selecting the DBI feature in DDR4, SSN shouldn’t be a bother in your design. If you’d like to learn more about SSN and similar challenges, check out our white paper “DDR4 Board Design and Signal Integrity Challenges,” which was recently nominated for the DesignCon Best Paper Award.

17 June, 2015

This is the second post in a three part series that will examine the problem of SSN and explore methods of reducing SSN in your designs.

In the first installment of our blog series on Simultaneously Switching Noise, we went through an overview of SSN and explained its relevance to high-speed parallel busses such as DDR4. This time, we’ll be taking a closer look at the effects of a poorly designed Power Distribution Network (PDN) on SSN and signal integrity.

Effects of a poorly designed PDN

To illustrate the effects that a PDN can have on signals, consider a setup of a single DDR4 byte lane running at 2400Mt/s with each signal running a unique random sequence. In this simulation setup, the package capacitor is not loaded. This removal of a major source of power for the higher frequency transitions (artificially) exacerbates the SSN effect.

Figure 1 Poorly designed PDN

Figure 1: Poorly designed PDN

In Figure 1 above, the eye for DQ0 does not have a lot of margin around the eye mask. This is not a very good situation.

Bad PDN: Worst-Case Switching

We can see the situation get worse if instead of allowing each signal to have a unique random sequence, they all switched with the same sequence. This way, we can see the worst-case effects of SSN—that is, when all the signals are toggling in unison and placing a great deal of strain on the voltage rail.

Figure 2 Worst-case bit pattern with a poorly designed PDN

Figure 2: Worst-case bit pattern with a poorly designed PDN

As can be seen in Figure 2, the eye for DQ0 gets a whole lot worse if all the bits are toggling with the same data pattern. In this case, this causes the eye to get closed.

Improving the PDN

Next, let’s insert the 4.7uF package capacitance which was removed to begin with. This should be a low-ESR capacitor and should be placed so that the inductance-causing loop area is minimized.

Figure 3 Worst-case bit pattern with improved PDN

Figure 3: Worst-case bit pattern with improved PDN

In this setup, all the signals continue to toggle with the same bit-pattern. So, this is the worst-case situation with the package capacitor inserted. This DQ0 waveform in Figure 3, while better than that generated without the package capacitor in Figure 2, is only barely passing the eye mask.

In a more realistic situation, the signals would indeed be independent of each other. Using unique random bitstream for each signal, we get the DQ0 eye shown in Figure 4.

Figure 4 Unique, random bit patterns for all signals with improved PDN

Figure 4: Unique, random bit patterns for all signals with improved PDN

The DQ0 eye improves dramatically. The smallest eye height in the mask region is now 275.5mV, better than the 211mV eye-height in the setup with the package capacitor where all the signals switch identically (Figure 3) and better than the 237mV eye-height with the setup where the package capacitors have been removed but the signals toggle independently of each other (Figure 1).

What we can gather from the above data is that the eye can be improved by adding appropriate package capacitors, or by ensuring that signals don’t all toggle identically. Ensuring that all the signals don’t toggle identically is one of the benefits of enabling the Data Bus Inversion (DBI) option in DDR4.

We will conclude the blog series next week by speaking more on the DBI option in DDR4. In the meantime, if you’d like to learn more about SSN and similar challenges, check out our white paper “DDR4 Board Design and Signal Integrity Challenges,” which was recently nominated for a DesignCon Best Paper Award.

2 June, 2015

This is the first post in a three part series that will examine the problem of SSN and explore methods of reducing SSN in your designs.

Digital designers have become accustomed to signal noise coming in from all directions. With the data rates running on the faster parallel busses, designers will now also need to be concerned about the noise coming out from the chip itself. One such kind of noise, Simultaneously Switching Noise (SSN), occurs due to the Simultaneously Switching Output (SSO) of buffers on a driving chip.

What causes SSN?

When a driven signal inside the chip transitions states, it consumes power from the rail. If a sufficient number of signals switch simultaneously, the rail might droop due to an inadequate access to immediately-required charge to provide current for all the switching outputs. This could happen because the capacitors from the Power Distribution Network (PDN), which are providing the charge, are too far away, or because those capacitors have been laid out in a way which causes them to have a high series inductance.

Subsequently, this droop in rail voltage causes the drivers to not drive clean signals. This is similar to crosstalk-induced noise in that the switching of one signal can cause variations in the output of another signal.

Accurately simulating the current draw of one driven signal on the voltage rail and the subsequent effect on other drivers requires information regarding the buffers’ behavior. One option would be to use Spice models. Alternatively, IBIS allows simulations which are much faster than Spice at a comparable level of accuracy, and is therefore a popular standard for simulation. IBIS 5.0 supports the data structures needed to simulate this “power-aware” topology.

IBIS 5.0's Power-aware Features

IBIS 5.0’s Power-aware Features

SSN is particularly relevant to high-speed parallel busses such as DDR4. With parallel busses, each bit can act independently of the others. This can cause greater loads on the power rails when the signals all switch in unison, creating a greater load on the rail.

In the second installment of this blog series, we’ll take a look at the effects of a poorly designed PDN on SSN and signal integrity. In the meantime, if you’d like to learn more about SSN and similar challenges, check out our white paper “DDR4 Board Design and Signal Integrity Challenges,” which was recently nominated for the DesignCon Best Paper Award.

17 February, 2015

A long time ago, when DDR first came out, some of you may remember that it was difficult to design the interface. In my old board design team, we simulated the interface quite a bit to make sure that the system would function when the boards came back.

Then of course, the “been-there-done-that” attitude set in, and DDR became a design-by-numbers interface to push the schedule. Then came DDR2, which had many similarities to DDR.  By the time DDR3 came out, many people didn’t even bother to simulate the setups at some of the slower speeds. They’re largely leveraged from a previous design, so why bother?

And then comes DDR4.  This is the new guy in town who you can sense is a bit different. Questions come up:

  • What, you don’t have a fixed Vref? 
  • You’re going to have a new threshold every time you power up? Then how do you know whether you’re the signal is a 1 or a 0 if I don’t know what the threshold is beforehand? 
  • What do you mean you’re going to flip all the bits?

Then maybe it starts to sink in:

Maybe I should simulate this. So, just how good are the IBIS models for this anyway?  Can I trust them at these higher speeds?

HyperLynx DDR4

These are many of the questions we answered, along with our partners at Fujitsu and Micron, in the paper that has was nominated at DesignCon for a best paper award: DDR4 Board Design and Signal Integrity Verification Challenges

In the first half of the paper, we discuss the details of DDR4.  What exactly are Pseudo-Open Drain (POD) and Data-Bit Inversion (DBI), and why the Vref is so dodgy?  It will give you good background information about how DDR4 is different from DDR3.

In the second half, we compare the simulation results of a large setup between the older IBIS 4.2 spec, the newer IBIS 5.0 spec, and a transistor level Spice model.  Spoiler alert: the IBIS 5.0 results very closely match the transistor level Spice models – at a small fraction of the time needed to simulate.

SPICE Net Model vs IBIS 5.0 Model (HyperLynx)

If you are designing a DDR4, and would like to confirm your board, this paper is a helpful reference in deciding what needs to be analyzed before and after releasing the board.

Download your copy of the paper here.

12 November, 2014

For most busses, length-matching a group of signals to 5 mils is a bit of overkill.  But, if length-matching to 5 mils is as easy for your layout personnel as length-matching to 100 mils, why not get the extra margin?  However, for very fast serial links, length-matching the two sides of a differential pair is absolutely crucial.  That is one of the key steps I discuss in my article “Ten Steps to Ten GigHertz“.
But length-matching the total length to a tight tolerance isn’t the only length-matching requirement.  Of course, the two halves of a differential pair need to be tightly length-matched so that both halves of the signal arrive at the same time.  But it is also important that the two halves of the signal travel together as well – in other words, the + and – signal should be in phase with one another throughout the route.  That means at any given location, the trace lengths are matched.  This is especially important at vias, where the matching of the signals is incredibly important to ensure that the signals pass through the vias in a purely differential mode, as this will limit the amount of energy radiated by the signals, as well as limit the amount of noise that the signals pick up.  This is especially crucial for 10GHz signals where margins are very tight.
This type of length-matching can be achieved by using phase-matching routing, like that implemented in Xpedition VX.  My colleague Charles discussed this the other day in his blog.  Click here to take a look if you are interested.

6 November, 2014

My grandma always told me not to sweat the small stuff, and since she just celebrated her 100th birthday, I am inclined to take her advice.  Unfortunately, that advice does not extend well to 10GHz serial links on a PCB, where you really DO need to sweat the small stuff.  With edge rates on the order of 50ps (that’s about 300 mils long on a PCB), 10GHz signals get affected by almost any discontinuity on a board, even those less than 100 mils.  So, special care must be taken to ensure that the entire differential path is free from discontinuities.

The biggest discontinuity faced by a 10GHz signal is a via.  That means your differential via pair must be designed to as close to 100ohms as possible.  This can be achieved by using smaller barrels, removing non-functional pads, and spacing the vias an appropriate distance apart.  The best way to design and simulate a differential via pair is by using a full-wave 3D electromagnetic simulator, like the one integrated into the LineSim GHz via modeler.  Minimizing or preferably eliminating via stubs is also an essential part of the design.  This means selecting the right routing layers, or employing the use of backdrilling, or even using blind and/or buried vias.

I discuss this and other topics related to the successful implementation of 10GHz serial links in my article “Ten Steps to Ten GigHertz“.  Take a look if you are interested in learning more.

5 November, 2014

When designing the trace configuration for your differential pairs, you are typically targeting 100 ohms differential.  That means each trace would be a 50-ohm trace, if there were no coupling between the traces.  But, you usually want some decent coupling between the traces, so a good single-ended impedance target for each trace is between 60 and 75 ohms.  That means that the differential pairs will have the highest-impedance traces on a given layer.  That also means they will have the narrowest trace width.  Typically that trace width will be 4 or 5 mils, to maximize routing density while maintaining a reasonable design cost.  However, differential pairs are typically running very fast, in the GHz range, so a very narrow trace width can limit the length of the pair to just a few inches.  By using wider traces, the copper losses can be reduced, allowing the differential pair to be routed over a longer distance.  However, wider traces also mean thicker dielectrics to maintain a 100-ohm differential impedance, and thicker dielectrics mean more spacing from other signals is required to minimize crosstalk.  So, basically, loss and routing density are at odds.  This can be offset somewhat by using a lower-loss dielectric, but the cost of doing so might be more than just adding additional layers to make up for the loss of routing density.  This is where high-speed analysis and simulation can be of great benefit in allowing you to make the right design tradeoffs.

I discuss this and other issues of working with high-speed differential pairs in my article “Ten Steps to Ten Gigahertz“, in Printed Circuit Design and Manufacture magazine.

9 September, 2014

I have recently been blogging about signal and power integrity, how the two are related, and how they can cross over.  This was prompted by an article I recently wrote for the DesignCon branch of EDN.  Twenty years ago, one of the biggest barriers to designing high-speed PCBs was ensuring signal integrity.  About ten years ago, power integrity started becoming a serious issue.  So what is next?  Is there another type of “integrity” we need to start analyzing?

No – at this point we pretty much have everything covered.  No more integrities on the horizon.  But what likely will change is how much we analyze in each of these analysis types…  For instance, if we look at vias, they used to be short enough to just model as a simple capacitor, then a simple L-C, and now for high-speed differential signals we need a full-wave 3D EM model of the via to properly characterize it for simulation.  For single-ended vias, we need to know the entire PDN to get an accurate signal model for the via.  And that is another trend that is permeating analysis needs – the impending crossover between signal and power integrity.  Eventually integrity analysis will encompass both, as well as other disciplines, all on the way to being able to create “virtual prototypes” of our PCBs, being able to predict their performance in a number of realms before the first prototype is manufactured.

8 September, 2014

There are a lot of reasons to mix SI and PI analysis – trying to figure out a worst-case stimuli to determine PDN performance, trying to see the effect of a poor PDN on signals due to SSN issues, or just being able to properly analyze a single-ended via.  In fact, to get an accurate model of a single-ended via, you have to mix SI and PI.  The reason is that the power distribution network, or PDN – decoupling capacitors, stitching vias, and plane pairs – make up the signal return path for a single-ended via, thus determining the “impedance”, delay, and crosstalk characteristics of the via.  This is especially crucial when modeling very fast, single-ended signals like DDR3 and DDR4 signals.  In HyperLynx, you can extract via models which include the PDN; this is achieved by the PI engine running in the background during the via model extraction.  The result is a very accurate wideband single-ended via model that properly captures the via’s electrical characteristics.  Once extracted, this model can be used in other simulations again and again.  Another option is to use the SI/PI co-simulation option, which generates these models on-the-fly.

To learn more about mixing SI and PI, take a look at this article in EDN:
http://www.edn.com/design/designcon/4433827/Signal-integrity-and-power-integrity-in-high-speed-design

3 September, 2014

Power integrity (PI) is an analysis discipline that has been around for years.  Signal integrity (SI) has been around for a few more years.  Basically, they both deal with the proper analog operation of digital circuits.  So why these specific realms of analysis?  The main issue is that there is no such thing as “digital” – what we call “digital” data transmission is really just voltages compared to thresholds, so making sure we have the right voltages at the right times is the essence of signal integrity.  Power integrity is a bit more broad in its scope, but a “power integrity” failure usually leads to the same results as a signal integrity failure – some kind of erroneous data.  It is tempting to try to analyze everything in a PCB design as one big “virtual prototype”, but modeling and computing limitations keep that from being practical.  Furthermore, the design process is made a bit easier by dividing up these problems.  For instance, a signal integrity problem can be solved by changing the line impedance, adding termination, or adjusting spacing to control crosstalk.  It is helpful to be able to analyze just the signal integrity of a circuit to look for these types of solutions.  Similarly, for power integrity, possible solutions might be adding more metal to control a DC Drop problem or changing the way capacitors are mounted to improve the PDN performance at higher frequencies.
For more information, check out the following article in EDN: Signal Integrity and Power Integrity in High-Speed Design.

Whatever your chosen flavor of integrity, be sure to simulate it early in the design cycle, otherwise you might get left with a bad taste in your mouth…

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