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Last week at DesignCon 2013, I provided an Analysis Anchored to Reality presentation of the highlighting and validating the new features of HyperLynx 9.0. Teledyne LeCroy, Molex, CCN, and Picosecond Pulse Labs partnered with us to provide measurement equipment, hardware to test, and a pattern generator for this demonstration. We started off with a correlation study so customers could see that the analysis results matched reality. This live analysis was performed in two steps.
First, I used HyperLynx 9.0 to create a virtual prototype of the multi-board system which included 2d and 3d models for the trace interconnect, via’s, and connector models. Using this virtual prototype of the passive channel I generated an s-parameter model for the entire channel. We then correlated this passive channel model to the measured s-parameter model. Next, I showed the time domain analysis in which we looked at the bath tub plots and the eye density plots to correlate it to the measured data.
Take a moment to watch my entire demonstration during an interview with
Mark Thompson on PCBDesign007.
Senior Product Marketing Manager
Over the past 16 years I’ve had the pleasure of being part of the development of HyperLynx and am excited about the latest release, HyperLynx 9.0 as we are simultaneously celebrating its 25th birthday and 10th year with Mentor Graphics.
HyperLynx was founded in 1988 when cell phones were the size of a lunch box, FPGAs were just hitting the streets with a Xilinx 2064 touting 64 logic cells, VHDL and Verilog usage was basically zero and Intel was yet to announce the 486. Things have definitely changed since then and so has HyperLynx. Our first tool, LineSim for DOS, was developed during nights in a basement in Redmond, Washington by Steve Kaufer and Kellee Crisafulli who at the time worked at Data I/O.
Today, HyperLynx has grown to be a comprehensive product line of tools that includes advanced SERDES channel analysis, AC and DC Power Integrity, Full DDRx Signoff Verification, Electrical Design Rule Checking, and Full-Wave 3D Electromagnetics for model generation of discontinuities. HyperLynx has become the best solution for SI, PI, thermal, and 3D EM simulation and analysis widely used by electrical engineers and PCB layout designers around the world. As our customers push the performance of interconnects, this need requires more accurate results much sooner in the process.
HyperLynx 9.0 is one of the fastest releases to date with more than 50 new and improved features on advance 3D channel and trace modeling, improved DDR sign-off verification and accelerated simulation performance up to five times faster, here’s why:
- The Fastest Simulator in the Industry
- State-of-the-Art 3D Planar Trace Extraction Technology
- For accurate modeling of signal path discontinuities
- Extensive Results Reporting
- So you can understand your exact timing margins
- Batch Extraction of S Parameters
- For performing multiple channel simulations
- DDR3L/U Support
- Mentor provides the latest device support
- DDR Wizard Enhancements
- Give you more measurements for more accurate simulations
These key benefits with HyperLynx 9.0 will increase accuracy in your simulations for faster time-to-market, fewer spins, and higher quality results. By getting the right PCB analysis technology, you will be able to deliver faster, higher-bandwidth-interconnect products your customers demand. For 25 years, the Mentor Graphics HyperLynx team has proven they can deliver the technology when you need it! The new release will ship in March 2013 and will be interfaced with all major PCB layout tools including Mentor’s Expedition Enterprise, Board Station, PADS, Cadence Allegro and Zuken CR. For more information about HyperLynx 9.0, visit mentor.com/hyperlynx and be sure to take a moment to watch the anniversary video on the HyperLynx YouTube channel.
If signal integrity engineers had the power to make their jobs as easy as possible, every signal in an electronic device would have its own coaxial cable to connect driver to transmitter. But then electronics would be the size of buildings again and certainly wouldn’t fit in your pocket. So instead, we try to cram as much stuff as possible onto a little PCB and make it work at 100s and 1000s of MHz. And, for the most part, we are successful, even when faced with cost reductions and crazy form factors that make our jobs even harder.
A consequence of that is trying to control all the coupling that occurs between signals, and to the outside world. Something like a via transition makes that really hard to do. Ideally, every signal via transition would be surrounded by as many vias as possible, all conected together to mimic the shield of a coaxial cable. But that is pretty unrealistic, so we usually add a couple of transition vias around the signal via. Some people only add one, and some don’t add any!! How many do you need? Well, you can answer that by running SI-PI co-simulations using Hyperlynx SI/PI. It allows you to experiment with different configurations of stitching vias, or stitching capacitors (necessary if the via is transitioning between layers that reference different planes of different voltages). Once you’ve determined what configuration works for your stackup and your signals, you can use the Vertical Reference Plane Change DRC in HyperLynx DRC to verify that it was done correctly, and that your board will be free from all the coupling that occurs from signals transitioning through vias.
Read this article to find out more: http://pcdandf.com/cms/component/content/article/171-current-issue/9656-designers-notebook
One of the nice things about newer, faster busses like DDR3 and DDR4 is on-die termination. They are nice because you don’t have a bunch of components clogging up your routing layers, and I would say more importantly, it limits your required layer transitions which can help make your boards quieter. So take advantage of the fact that you don’t have to route out to a terminator and try to keep your layer transitions limited to underneath the IC. The area under the IC is a particularly exciting location on the board, and also happens to be the best place for layer transitions.
In a recent aricle in Printed Circuit Design and Fabrication Magazine, I discuss the EMI problems associated with layer transitions. The article can be found here: http://pcdandf.com/cms/component/content/article/171-current-issue/9656-designers-notebook
Bascially, a stitching via is needed anywhere you transition a signal between layers, to provide a continuous return current path for the signal. I have discussed return current paths in several previous blogs, but to summarize, broken return path = radiating signal. This is why a stitching via is needed when a signal transitions between layers. Well, more precisely, a stitching “thingy” – in the case that the different return paths are planes with the same voltage (usually ground), a via will work. But if they are at different potentials, a capacitor should be used. Where on the board are there the most vias and capacitors? Just around the IC. This makes it the best place to do any layer transitioning.
In the past I have blogged about crossing splits in reference planes. This is probably the most glaringly obvious of reference plane changes, and will of course result in radiation from the signal.
But another type of reference plane change which is more common, and usually much less avoidable, is when a signal transitions layers through a via. In such a case, the reference planes will change and the return current will need to find a path to accomodate the change. This is probably best explained with a picture, which can be seen (along with a more complete explanation) in my recent article in PCDandF: http://pcdandf.com/cms/component/content/article/171-current-issue/9656-designers-notebook
This problem is most severe for very fast, single-ended signals like DDR3 or DDR4, which will have all their return current present in their reference planes, and require a very close-by stitching via (or capacitor) in order to ensure minimal radiation of signal energy and minimal resulting signal degradation. The further away the stitching via (or cap), the more energy that will radiate and the more degraded the signal will become. SERDES signals, although much faster, also happen to be differential, which means that they tend to have mostly self-contained, zero net return current (since they consist of equal and opposite signals).
So, every time you transiton between signal layers, try to add a stitching via as well. If you are wondering how many un-stitched transitions you have in your design, run the Vertical Reference Plane Change DRC in HyperLynx DRC and it will find them for you…
In previous blogs, I have discussed the importance of an uninterrupted, intact reference plane for signals. But, what if you have two reference planes for your signal? This is probably true of most signals in any board over 6 layers – a great deal of routing exists on the inner layers.
In a symmetrical stripline, the return current is shared equally between both planes. So, both planes need to be solid.
Often, however, a “dual stripline” structure is used to squeeze in as many routing layers as possible into a board stackup. Most dual striplines have a large gap between the two signal layers to minimize layer-to-layer crosstalk, which prompts the question: do I need to worry about the further reference plane? In order to answer that question, you need to understand that return current scales linearly with the distance to the planes. So, if I have a dual stripline structure where the signal layers are spaced 4 mils from their nearest reference plane and 12 mils apart, that means I have a 4:16 ratio of distances to reference planes for the signal layers (if I neglect the copper thickness of the signal layers), which reduces to 1:4. That means that 80% of the return current will go into the nearer reference plane and 20% will go into the further one. I discuss this (with pictures!) in the following article:
In HyperLynx DRC, you can set a threshold for the required percentage of return current in a plane to include the plane in the check, for DRCs like the Nets Crossing Gaps DRC and Reference Plane Change DRC. It’s a great way to ensure that you don’t have large amounts of current radiating into your EMI chamber!
Okay, well, I guess you could say “it depends”, but in general, no, it is not okay to cross a plane split.
Basically, you are creating a break in the current return path for the signal. That turns your trace/plane combination into more of an antenna than a transmission line. And if you are radiating energy, that means you are not transmitting energy to your receiver. So, it can lead to EMI issues as well as signal integrity issues.
I discuss this more in the following article:
What about slower signals?
Generally, plane splits cause the most severe problems on faster single-ended signals, like DDR2/3/4. Slower signals (more specifically signals with slower edge rates) have less problems crossing splits, because the return current can usually find an alternate path, and the signals are slow enough that that path can be relatively long. But crossing splits also makes signals more susceptible to noise, so if you have a sensitive “slow” signal like a reset, this can still cause problems.
What about connecting the planes with a cap?
Bridging the plane split with a bypass capacitor can help some, but there are some caveats. First of all, it is important to remember that a mounted capacitor is a narrowband structure – it only acts as a low impedance across a limited frequency range. Also, you would need a bypass capacitor for every signal that crosses the split, otherwise the signals will share return paths and show a marked increase in crosstalk.
Trying to mitigate all the problems caused by crossing plane splits ends up being lot more work than just planning ahead to eliminate them from your PCB design. So, just say no to crossing plane splits.
Many electromagnetic interference (EMI) problems on PCBs happen when antennas are unintentionally created on the board. How can this be avoided? By making sure currents, especially high-frequency currents, travel in a loop. On high-speed lines, that loop is made up of a PCB trace AND the reference plane below it. Put a break in either one, and you’ve created an antenna. Obviously you would never consider breaking a signal trace, so why have a break in its reference plane?
I discuss this in greater detail in a recent article in Printed Circuit Design and Fabrication Magazine: http://pcdandf.com/cms/component/content/article/246-2012-articles/9315-pcb-design
Avoiding such cases on very complicated designs with low layer counts requires some planning early in the design cycle. Different busses should have their layers pre-determined and should be routed adjacent to ground and/or their associated voltage planes. Otherwise, a trace could get routed across a plane split, which is a break in the reference plane that can cause EMI issues. Even with careful planning, signals may still end up getting routed across splits. Or, large gaps in the reference plane may get created from neighboring antipads or other similar structures. These issues can quickly and easily be pinpointed with an electrical rule checker like HyperLynx DRC (http://www.mentor.com/products/pcb-system-design/circuit-simulation/hyperlynx-drc-emi-emc), and the issues resolved before the board gets fabricated. Trying to fix these kinds of issues on a fabricated board in the lab is next to impossible.
For SERDES channel designs, board/system designers are told to remove stubs and non-functional pads (NFP) of vias on channels to ensure signal quality at the receiver ends. What confuses them the most is when to consider these effects: does one have to remove all NFPs and stubs in any channel carrying signals with data rates over 1Gbps? Can a design still work even if via stubs are kept?
The actual consideration here should be the channel budget. An interface specification usually requires the insertion loss (in dB) of an entire channel within a pre-defined margin at or below certain frequency points. This is the allowed noise budget of the channel. (Note that the important concept here is not data rates in time domain, but frequencies in frequency domain.) As an interconnect component of a channel, via response generates noise, therefore, consumes the budget. If an existing channel carrying the signals with certain data rates has the overall loss within the required margin, the design will work and it is likely that a designer does not need to modify via designs, such as removing NFPs and stubs of vias. This is an important aspect for designers to understand: vias on a channel may have bad behavior but the effects may be out of the range that channel budget specifies; then no action is needed to make changes to vias.
Read this article to see the examples where the effects of NFPs and stubs may happen within the interested frequency range, and only then designers need to consider the possible signal degradation from vias.
Designers dealing with SERDES channels pay more and more attention to signal via effects. Many literatures and guidelines talk about the approaches to correctly configure vias so that via effects on signals can be minimized. Such methods require detailed analysis of single via or differential via pair. With the help of accurate 3D field solvers, vias can be designed to have controlled noise in channels by specifying stackup and padstack. One needs to know that such detailed analysis is for via structure itself, it does not consider any influence from other components on board. After the pre-studied structure is put on board with routed nets, placed components, and drilled holes, coupling occurs between vias and those components. Then, the previously understood behavior can be affected and extra noises may present. Therefore, the discontinuity effect from the particular via (or via pair) needs to be simulated again with its immediate neighbors, such as nets, other vias, etc..
We can see now that proper designs of vias on SERDES channel actually involve two parts: designing via configuration in pre-layout environment (design), and verifying via performance in post-route environment (verification). The first part explores design space at the early stage of a design, while the second part makes certain the pre-defined structure behaves as expected in the product. Designers need to perform 3D analyses at the beginning and end of a design, which the integration of 3D field solver in an SI tool is necessary. Read this article to get the details on the design and verification process with 3D field solver integration in SI environment.
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- Developing Confidence in Your Analysis Tool – HyperLynx 9.0 Demonstration
- Introducing HyperLynx 9.0: Fastest time to accurate results
- How much stitching do I need?
- Pick a layer and stick with it
- Manage reference plane changes for quiet boards
- Return current on a stripline
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