PCB Signal and Power Integrity Tech Corner
PCB Signal and Power Integrity Tech Corner RSSTurn off your phone!
Everybody knows you are supposed to turn off your phone and other electronic devices when you are on a plane. You can leave it on during the flight, but it has to be off for takeoff and landing. I like to remind people in case they “forget”. I tend not to make a big deal during takeoff, but landing has me a little more on edge.
The problem is coupled noise. Sure, most modern planes should be designed such that some electronic interference in the cabin should not affect the plane’s electronics, but you never know. And is it worth the risk? I don’t think so. The thing that worries me most is the fact that many handheld electronics take some design shortcuts in order to minimize cost. Where many should probably use boards with 4 or more layers, often they will only use two layers. That means that the PCB traces, instead of coupling noise onto a solid plane (no pun intended (seriously, I meant an actual ground plane (no, not a grounded plane (although that could be the result) but an actual solid sheet of copper in the PCB (which yes, should of course be grounded, anyway, I digress….)))), are coupling noise out into the world. Such coupling is a special kind of “crosstalk” commonly referred to as electromagnetic interference, or EMI. It is but one of the many mechanisms that unwanted noise can get coupled from one place to another in electronic designs. You can read more about noise coupling in the following article:
http://pcdandf.com/cms/component/content/article/171-current-issue/8973-designers-notebook
And please, turn off your phone when you are on a plane (more precisely, an airplane) during takeoff and landing. Unless you can see the radiated emissions (which you can’t, even if you squint) you won’t know they are there.
And speaking of radiated emissions… well, no, that’s really the subject for another blog. It has to do with restricting airport restaurants from serving beans…
Tags: coupled noise, crosstalk, HyperLynx, noise coupling
Is it SSN or is it Crosstalk?
In the lab, both simultaneous switching noise (SSN) and crosstalk look the same. They appear as unwanted pulses of energy that line up with the (aggressor) signal edges. However, the mode of energy coupling is much different between SSN and crosstalk. In the case of crosstalk, they are lining up with the edges because the signal edges are coupling energy onto the victim signal through electric (and magnetic) fields. This occurs from one trace to another, and increases the closer those traces are. SSN, however, couples noise through the power distribution network (PDN). If the impedance of the board PDN is too high at the IC power pins, the switching current of the I/O buffers will induce a voltage onto the other I/O lines. And because these current demands occur as the signals are switching, the resulting SSN appears as a pulse that lines up with the signal edges.
How can these two phenomena be distinguished? Well, in the lab, you could try to toggle only the nearest two bits to the victim signal. Most of the crosstalk on a single layer will come from the nearest two aggressors. And with only two bits toggling, if the problem is indeed SSN, there should be a significant reduction in the coupled noise. The easier solution, however, is to run SI and PI simulations during the design phase to ensure such problems are avoided in the first place.
To learn more about various sources of noise coupling in your PCB designs, and how to prevent them, take a look at this article:
http://pcdandf.com/cms/component/content/article/171-current-issue/8973-designers-notebook
Tags: crosstalk, crosstalk v SSN, HyperLynx, simultaneous switching noise, SSN
Crosstalk is everywhere
Crosstalk is everywhere. Really, in a more general sense, noise coupling is everywhere. Usually the method of noise coupling is traditional “crosstalk” – the unwanted transfer of noise from one place to another through coupled electric fields. This most often occurs on PCB designs with dense routing, and on wide parallel busses. Even on newer SERDES busses, however, it is still an issue, as many such busses have multiple lanes, such as PCI Express. And crosstalk is also an issue on SERDES busses when they are routed close to slower, much higher voltage signals such as 3.3V and 5V signals. Crosstalk can also occur in a similar fashion between higher-voltage switching power supplies and sensitive lines like resets.
But it is not only crosstalk that causes noise coupling. Shared return paths are another common method of noise coupling. This occurs most often in connectors without sufficient ground pins. Since ground pins act as the return paths in connectors, an insufficient number of ground pins will cause shared return paths and hence coupling between signals travelling through the connectors. A similar type of situation can occur in boards without enough stitching vias near signal layer transitions.
And coupling can also occur through the PDN. An inadequately designed PDN can directly result in simultaneous switching noise, or SSN.
All of these coupling problems can be identified and resolved through simulation in HyperLynx.
To learn more about how to control this noise, take a look at this article:
http://pcdandf.com/cms/component/content/article/171-current-issue/8973-designers-notebook
Tags: connector crosstalk, crosstalk, HyperLynx, noise coupling, SSN, via coupling
The cure for sick waveforms
Found a signal integrity problem in the lab? How do you go about fixing it? Well, if it’s a SERDES bus, you can’t do any kind of re-work because it will most likely kill the signal even more. Maybe you can play with some driver strength or pre-emphasis settings. Or is it a slower, parallel bus? Maybe you can re-work in some necessary termination. This is where post-layout SI simulation is useful. In simulation, you can mimic the problematic situation, and try to figure out a solution, without even touching a soldering iron. And what’s more, you can simulate all the nets on the board to make sure they don’t have similar problems.
In fact, you wouldn’t be in such a situation if you did a full-board SI verification before sending it to the fab house. Better yet, if you did some pre-layout simulation to identify the necessary constraints on the critical busses, there may not have even been a problem to find in post-layout simulation. In every step of the design phase, changes become orders of magntiude more costly and time-consuming. That’s where doing the bulk of your signal integrity (and power integrity) work towards the beginning of the design cycle really pays off.
You can read more about it here:
http://electronicdesign.com/article/eda/whats-difference-prelayout-postlayout-pcb-simulation-73640
Tags: HyperLynx, post-layout, pre-layout, signal integrity
Running at 6GHz with your eyes closed can be scary
Running at 6GHz is actually kind of scary regardless, but especially so with your eyes closed. And I mean that more figuratively than literally. Obviously, if your eye diagrams are closed on your serial links in your design there is cause for fear, but the fear of the unknown can be even greater, especially if you are running at multi-GHz speeds. That is where a complement of pre-layout and post-layout signal integrity simulation can help.
Take a look at this article discussing the differences: http://electronicdesign.com/article/eda/whats-difference-prelayout-postlayout-pcb-simulation-73640
Pre-layout simulations are a great way to see if a design is even feasible. For instance, if you are trying to run a 6Gbps link like Serial ATA or SAS through several boards and a long backplane, it might not make it unless you make the appropriate choice of connector, board stackup, and trace geometries. Pre-layout simulation is a great way of gaining an understanding of the limitations of a certain bus architecture, and understanding the margins of your system. This opens your eyes to what your design is actually doing. It also leads to a better understanding of what might be a potential problem once the system is built. In fact, post-layout simulation is even more useful in that regard, as it gives the most accurate view of what is going on at the receiver. Post-layout simulation is often more useful than actual measurement. Multi-GHz busses cannot be measured while they are running; they usually need to be measured into some sort of test fixture. So, having a post-layout simulation handy to see what is going on in the actual design, including the effects of equalization at the receiver, is invaluable.
Tags: 6GHz, HyperLynx, post-layout, pre-layout, SAS, SATA, signal integrity
It’s never too late
It’s never too late to fix a design problem. Well, maybe if the product is shipping, that might be classified as “too late”. But during the design phase, whether you’ve laid out your board or not, it’s a good time to make sure there are no design issues. When it comes to signal integrity, that means performing pre-layout or post-layout simulations. I think most experts agree that pre-layout simulations are the best time to do signal integrity. There those, however, that feel pre-layout simulations are a lot of time wasted on “what might be”, but the counter-argument is that if you don’t simulate, how do you know what constraints to apply to your board layout as it is being layed out. I say as long as you do EITHER before the product ships, you’ve done well. But, when it comes to getting products out in the fastest and most efficient manner, a mixture of both pre-layout and post-layout simulation will best suit your needs.
What’s the difference? Well, other than the obvious fact that post-route simulations are done after layout, I would classify the main difference as the fact that pre-layout simulation is aimed more at exploring a solution space and creating design constraints, while post-layout is aimed at verifying that those constraints were met. For a more in-depth discussion on the differences, take a look at this article in Electronic Design magazine:
http://electronicdesign.com/article/eda/whats-difference-prelayout-postlayout-pcb-simulation-73640
Tags: HyperLynx, post-layout, pre-layout, signal integrity, simulation
Put the Pieces in Place for SERDES Success
Interconnect loss modeling? Check.
Signal conditioning modeling? Check.
Ability to simulate multiple S-parameter models for things like connectors and packages and vias correctly in the time domain? Oooh…. that’s a tough one. Check!
Ability to include all sources of deterministic and random jitter, worst-case bit patterns, and worst-case crosstalk in the analysis? Wow! Check.
3D via modeling? Check!
HyperLynx 8.2 is fully equipped to handle every SERDES problem you can throw at it. Really, any signal integrity problem you can throw at it. Power integrity too.
In general, SERDES designs are a lot easier to implement than parallel busses. You have a smaller number of problems to worry about, but the problems that are there are considerable. They are basically problems of fast edges and low margins. The fast edges require careful attention to detail in all aspects of the layout, and bring about the need to analyze pieces of the interconnect that could be ignored with slower edges, most notably vias. And the low margins necessitate a greater understanding of when the bus will actually fail. So in order to be successful in the analysis of these busses, care must be taken to include everything that is needed to understand the limits.
Read more about it in my recent article in New Electronics magazine:
http://www.newelectronics.co.uk/electronics-technology/the-challenges-of-designing-high-speed-interfaces-at-the-board-level/40549/
Tags: 3D via, BER, channel analysis, crosstalk, equalization, HyperLynx, interconnect loss, pre-emphasis, SerDes
Know your limits
“A man’s got to know his limitations” … true, and so does a digital bus. Clint Eastwood’s quote to conclude the movie Magnum Force in 1973 also applies to digital busses. Of course, back then, signal edge rates were slow enough that most people didn’t have to care too much about signal integrity. And now, in sharp contrast, we’ve progressed to the point where we try to validate busses down to bit error rate (BER) levels of 10^-15. And things are moving so fast now that you can’t rely on measurement to know your margins, or your limits. Even parallel busses like DDR3 require simulation in order to appropriately understand the margins of the bus. Probing at the pin on such busses yields little more than very ugly waveforms, so simulation allows a unique perspective into the limits of the bus.
For SERDES busses, this is especially true. With receiver equalization becoming very common, it is very important to know what the signal looks like inside the IC. And, in order to ensure the bus will work to the required performance standards, you have to run simulations that predict performance for trillions of bits, and include effects of deterministic and random jitter.
You can read about this in greater detail in my recent article in New Electronics magazine on page 25:
http://journal-download.co.uk/digitalmagazines//ne/ne28feb2012fullne.pdf
Tags: BER, bit error rate, DDR3, equalization, HyperLynx, SerDes
Shorter stubs are getting longer
…It all depends on how fast you are trying to go. That’s really the name of the game with anything signal integrity. The faster we go, the more “new” problems we face. Even if a stub were 50 mils long, if your edge rate is fast enough, such as the edge rates used in many SERDES busses today, it could be enough to fatally degrade your received signal.
At the beginning of my career, I worked a bunch on a bus called SCSI. Up to 15 hard drives all connected together on the same bus, each hard drive connection having around a 1″ stub (sometimes more). Luckily the fastest it went was 80MHz, but it was still a challenge from a signal integrity standpoint. Fortunately SCSI, like many other parallel busses, has been replaced by a newer SERDES architecture. SAS, or Serial Attached SCSI, is a lot easier to implement than its parallel predecessor, but presents some new challenges. No need to worry about 1″ stubs any more on the hard drives, but now layer transitions and vias actually pose the threat of stubs. For instance, on a 100-mil thick board, if you transition from the top layer to a middle layer using a traditional thru-hole via, the rest of that via will be acting like a stub, with a length on the order of 50 mils. This can severely degrade the signal, and should be modeled in simulation before creating the board design to ensure it is not overly detrimental. Depending on the speed, the via and its stub may require a model from a 3D field solver, which can be created in HyperLynx 8.2. To learn more about this and other aspects of via design, check out my recent article in PCDandF:
http://pcdandf.com/cms/component/content/article/171-current-issue/8439-designers-notebook
About PCB Signal and Power Integrity Tech Corner
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Latest Posts
- Turn off your phone!
- Is it SSN or is it Crosstalk?
- Crosstalk is everywhere
- The cure for sick waveforms
- Running at 6GHz with your eyes closed can be scary
- It’s never too late