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Challenge For Dynamic Flex: Impedance Control

June 26th, 2010, by | Permalink | No Comments

By Happy Holden, Foxconn Advanced Technology

 

One of the advantages of working for Foxconn is that it is now the worlds largest manufacturer of electronics products.  This brings us into contact with the worlds finest OEMs and their designs.  Understanding those designs provides a wonderful and rich learning experience, it also provides the opportunity for us to innovate on our own to improve those products and also lower their manufacturing coats or raise their yields. 

Dynamic Flex

Mobile phones are a big and growing part of our manufacturing.  Thus the problem of “high-speed signaling” across the ‘dynamic flex’ portion of a mobile phone is an important one for Foxconn.  As shown if Figure 1, four types of dynamic hinges are typically used on mobile phones:

§         Clam-shell type

§         Revolve type

§         Universal joint type

§         Slide type

 

This figure also provides some insight into the copper and PI thickness and usual structures for the flex.

 

 slide1

FIGURE 1: Four types of ‘dynamic flex’ for mobile phones with copper thickness, PI thickness and suggested structures

Impedance Control

The difficulty arises when very fast rise-time signals are needed between the main control board and other peripherals like the display.  For static pictures, there is no problem, but when video is involved, then transmission lines need to be employed. Here is only a partial list of signal interfaces flex is used for:

 

 IEEE 1394 (110 Ohm)

 PCI-Express Gen1 (100 Ohm)

 USB2.0 (90 Ohm)

 Video (90 Ohm)

 PCI-Express Gen2 (85 Ohm)

 Memory (75 Ohm)

 

 

 Problem is – - most transmission lines require a ‘opposing’ return reference and this solid ground plane impedes the dynamic flex and will eventually crack.  So two “modified differential-pair” transmission structures are employed.  Figure 2a & 2b show those 2 structures and 2c shows a new “Broadside-Coupled differential-pair” that Foxconn has developed.

 slide2

FIGURE 2: Three novel differential transmission lines for the ‘dynamic region’ of flex circuits  a. Edge-coupled differential microstrip with mesh GND  b. Co-planar differential microstrip w/o opposing GND   c. Broadside Coupled differential microstrip w/offsets

Three Innovative Structures

The three structures in Figure 2 are not the only ones, just some of the most popular and useful.  These three are:

§         Edge-coupled differential microstrip with mesh GND (Figure 2a)

§         Co-planar differential microstrip w/o opposing GND (Figure 2b) 

§         Broadside coupled differential microstrip w/offsets (Figure 2c)

Edge-Coupled Differential Microstrip with MESH GND

The  edge-coupled, differential-pair microstrip with the MESH GND, as seen in Figure 3a, is one of the most popular.  The MESH GND provide a Reference Return Path for signals but it distorts the fields set up by the high-speed signals.  To calculate the resulting impedance requires a 3D Field Solver instead of the normal 2D one used in rigid boards.  In Foxconn case, we use the 3D Solver from Computer Simulation Technology, AG (CST) to calculate trace widths, spacings and mesh parameters.  In Figure 3b, a 1 inch transmission line is modeled and seen in Figure 3c.  In this case, this has an E-field this is “Asymmetrical” that can result due to ‘mis-registration’ but also may be intended.  Mesh parameters can create as much as 5 to 6 ohms difference in the resulting differential impedance.

The effect of introducing a ‘MESH’ to the ground reference plane usually results in the differential impedance being increased.  Currently, the MESH GND is a new one of the high-speed models provided by Polar Instruments, just introduced.

 slide3

FIGURE 3: a. Mesh GND differential microstrip  b. a 1.0 inch simulated transmission line  c. Unbalanced E-field from asymmetrical spacing to Mesh  d. Symmetrical E-field from balanced Mesh

Co-planar Differential Microstrip w/o Opposing GND  

More conventional is the co-planar differential microstrip.  This is seen in  Figure 4a.  When used as the PCI-Express transmission line (Figure 4c), Figure 4b shows the resulting eye-diagram.   A 1.0 inch transmission line simulated is seen in Figure 4d. the symmetrical E-field for this ‘relieved’ co-planar diff. microstrip

 

There is no Polar model for the particular structure that Foxconn uses.  Polar has a 2B1A Model, “Diff Embedded coplanar strips with Ground and a 2B1A, “Diff Embedded Coplanar Waveguide” but Foxconn has the ‘opposing’ Guard Ground intrude to the edge of the trace field, or 3*d.  The difference in impedance between these two extremes is nearly 31 ohms.

 slide4

FIGURE 4: Co-Planar Transmission line without bottom GND   a. Structure  b. eye-diagram for the PCI-Express  transmission line in c.   d. simulation of the symmetrical E-field for this ‘relieved’ co-planar diff. microstrip

Broadside-Coupled Differential Microstrip w/Offsets

In order to avoid too thin of a dielectric and the resulting close spacing of signal traces to the lower ground plane that results in lower trace impedance, Foxconn removed the lower ground plane and routed the P/N signals on the upper and lower plane respectively.  This closely simulates a conventional ‘twisted-pair’ scheme, see Figure 5a. .

This new design scheme allows the changing of the offset distance (d) of the P/N signal lines on different layers  to match the requirement of the target differential impedance (Figure 5b). P/N signals continually exchange the routing layers at a specific distance, which mimics the twisted-cable-like routing.  Based on the proposed broadside-coupled, differential signal design, this extended design scheme is called “twisted differential-pair signals”. 

On the same layer, the current flow direction through Section 1 and Section 2  is inverse and can further suppress EM radiation (Figure 5c).

d (mil)

Zdiff (Ohm)A

Zdiff (Ohm)B

5

105

120.847

4.5

99

116.744

4

92

112.339

3.5

86

107.789

3

80

103.115

2.5

75

98.337

2

69.6

93.298

1.5

65

88.198

1

60.5

82.83

0.5

55

77.564

0

50

72.096

 

 

The only ‘downside’ is the “Via Effect” results in higher resonant frequency and a peak at 165 psec of +14 ohms  Given 100-ps TDR rise timeit can be observed the differential impedance of the twisted differential-pair signal is higher than the conventional broadside coupling one @ 3.5GHz.  Only over some frequency bands is the sdd21 of twisted broadside coupling scheme better.  Compared with differential mode return loss, common mode return loss shows larger reflection, which means more mismatch exists in terms of common mode impedance.  For Far-Field Radiation over 3-meters-Twisted differential-pair signal scheme shows better differential mode radiation than the conventional broadside coupling scheme.  Twisted dps scheme is a little worse than conventional broadside coupling scheme under 1GHz.  Twisted dps scheme is better than conventional broadside coupling scheme above 1 GHz.

 

Table1: Comparison of different offset distance (d) with resulting differential impedances for Polar calculation (A) and 3D Field Solver from CST (B).

 

Polar’s recommendation for simulation is to use a “Broadside-Couples Stripline 3S but change ‘Substrate-3’ dielectric thickness to be “Large (>40 mil)” and to change it’s dielectric constant to air (Dk=1.0).  This removes the ‘outside’ reference grounds from having a field effect and substitutes air for one of the plastics.  The Polar simulation can be seen in Table 1 compared to the 3D Simulation from CST.

 slide5

FIGURE 5: New design with offset broadside-coupled differential transmission lines.  a.  structure  b.  relationship of offset distance (d) and resulting impedance (Zdiff)  c. new design scheme:Change the offset distance (d) of the P/N signal lines on different layers  to match the requirement of the target differential impedance.

   Conclusion

 

 

 

Conventional Mesh Ground

Twisted Broadside Coupling Diff. Pair

EMI Suppression

Acceptable

Good

Measured TDR Impedance

Bad

Good

Common-mode Noise Suppression

Bad

Good

Routing Feasibility

Acceptable

Good

Table 2: Comparison of different design schemes to fix low impedances in dynamic FPCs

 

The proposed twisted broadside coupling differential pair, which combines the concept of the previously-published broadside coupling differential scheme, not only can precisely control  Transmission Line Impedance but also can further suppress EMI effect. As seen in Table 2, it has a number of advantages  over the conventional MESH GND approach.  This new proposal only adjusts the routing procedures without extra cost, and is therefore considered a cost-effective and novel solution.

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Technology Drivers For Printed Circuits-REVISITED

June 26th, 2010, by | Permalink | No Comments

BY:  Happy Holden, MIPBG-Foxconn, DaYuan, Taiwan 

 

In May of 2005 I wrote my column about the five (5) technology drivers I believe are important for printed circuits.  Five years later, it is a good time to revisit and see how those Technology Drivers are doing and “what has changed” in five years.  The five (original) drivers I believe are important for printed circuits are:

 

1.      Active components and IC technology

2.      Signal integrity and higher speed signaling

3.      Direct Material that make up the boards

4.      Design of printed circuits that capture the IP intent of electronics

5.      Process improvements for PCB manufacturing

 

Why Is This Important?

     I have to admit that I can’t think of a better list of Drivers after five years.  BUT…..the explanation of those drivers has changed in the last five years and that  may be of interest to readers.  You can retrieve the old column from www.CircuiTree.com if you want to see what I said in 2005, as I will not use valuable space here to ‘revisit’ that column.

 

Active Components and IC Technology

“The semiconductor industry is STILL the primary driver for electronics.  Smaller gate geometries and greater total gates allow more functions to be performed – and faster.  With larger wafers, the prices continue to tumble.  This allows and inspires more products that grow the entire industry.”  We (the West) are still the drivers of advanced semiconductor technology design but share fabrication technologies with the Asians.  Much of the foreign construction of wafer fabs that focused on commodity memory and glue chips, has now expanded to be the world’s “Foundries”.  IBM, Intel, Freescale, AD, Thompson, Samsung and Texas Instr. to name just a few are continuing to lead the IC industry worldwide.

 figure_1

 

FIGURE 1. The Waves of increasing interconnect density shows the effect of 2D to 3D stacking technologies. System-in-Package (SiP), Package-on-Package (PoP), Through-Si-Vias (TSV), Reverse Thru Via (RTV) and High Density Chip Carriers (IMBtm are leading to true 3D package integration.

This growing development continues to increase the interconnect density as seen in FIGURE 1.  But now we are moving to true 3D packaging with stacking and embedded ICs like the Imbera “Integrated Module Board” Technology. [1]

 

Signal Integrity and Higher Speed Signaling

      “Related to IC technology and smaller gate geometries is the increasing speed of signals.  This manifests itself not just in higher-frequency applications but also in shrinking signal rise-times.  Another resultant is higher heat dissipation and a resultant reduction in power supply voltage.  All of this conspires to increase the sensitivity of circuits to various forms of noise and loss of signal strength.”  While this is still true, what we also face NOW is “the return path for that signal” or POWER INTEGRITY.  The power distribution network (PDN) is increasingly important in high performance and high-speed signaling.

Since the PDN is now of such importance, there needs to be “Innovations” about PDNs on PCBs.  One way is to eliminate the conventional Power Plane and replace it with a newer-better-creature.  That is to use two, orthogonal layers to distribute PWR as a ‘Mesh Structure’ and to place signals between the different voltages.  This can be seen in FIGURE 2 and the structure is called a ‘Dual Offset Coplanar Stripline w/Separate GND Reference’.  Line widths and dielectric distances are given for the various impedances that are commonly used.  This structure has the advantage of lower crosstalk but more importantly, it provides voltage to all the components from ‘LAYER_2’ and LAYER_N-1’ using only a low-inductance, non-reflective blind-via.  [2].

figure_21

 

FIGURE 2, The Offset Coplanar Stripline offers a high-speed impedance model to distribute power and signal on two-orthogonal layers to not only improve density but improve the signal and power integrity while reducing crosstalk noise. [2]

 

Direct Material That Make Up The Boards

     “Laminates increasingly are paramount to high-performance PCBs.  Not just low loss laminates but also low dielectric constants (or consistent dielectric constants), as well as higher heat resistance that is needed for lead-free assembly processes.  With faster rise-time devices and lower power supply voltages, comes the need for lower power distribution networks impedances.  At high frequencies, this can only be achieved by reducing the distance between PWR and GND.  We have called this ‘buried capacitance’ (BC) but ‘distributed capacitance’ might be a better name.” [3] 

While there has not been any new distributed capacitance materials created in the last 5 years new lower Dk and lower Dj FR-4s and non-FR4s have been developed, along with the growing trend of halogen-free laminates.

 

Design of Printed Circuits That Capture The IP Intent of Electronics

“For to long it [PCB design] has been undervalued in its contribution to the electronics industry.  Now especially, when signal frequency and signal integrity are needed more and more, companies continue to undercapitalize their CAD tools, decline sending their PCB Designers to much needed training and conferences and undervalue Productivity Tools and Software to improve both the quality and speed at which printed circuits are designed.”

N.A. EDA vendor Mentor Graphics continues to invest in its PCB Design Tools PADS and EXPEDITION by not only increasing features and functionality, but adding more ‘seamless’ integration of signal/power integrity, FPGA optimization, BGA breakout and Design for Test and Assembly, as shown in FIGURE 3.

figure_31

 

FIGURE 3, This PCB design and engineering flow from Mentor Graphics Expedition shows the current stage of integrated tools for modern high-speed printed circuit simulation and layout.

 

Process Improvements For PCB Manufacturing

“With IC, circuit and material innovations comes the need for process improvements.  We excel in this material/process area.  Companies like DuPont, 3M, Kodak and others have let the world in process and chemical innovations.  Where once it was basic chemical and plastics, today it is pharmaceuticals and nano-technologies.  But the legacy is still there in companies like MacDermid, Rohm and Haas, OMG, Enthone, Atotech and many more.  The Japanese have done well here as well, but in a much more limited scope to support their consumer products.  The majority of processes that the Chinese are using to manufacture printed circuits is either North American direct, or licensed from N. Americans or possibly even duplicated from N.A. processes.  When these processes are in the laboratory phase, it is the myriad of smaller North American PCB facilities that do the pilot work on them and feedback valuable information.  Typically, it is the higher volume N.A. PCB facilities that first put them into volume production.  But being a global market, these process corporations have an obligation to their stockholders to also distribute their new processes to their customers in Asia.  Thus, printed circuit manufacturing today is one of managing the innovations of global corporation’s materials and processes.” 

While this is basically still true, the role of “Pilot Line” has shifted to the Asians.  That’s because the growth has been most dramatic in mobile/consumer, IC packaging and automotive electronic products where Asia dominates PCB production.  To support this, most major Process/Specialty chemical companies have moved their “Application Engineering and Development” to Asia.

 

Finally, I said “These five (5) Technologies, as well as many others not mentioned here, are the MEASURES OF EXCELLENCE that WE CANNOT AFFORD TO LOSE TO ASIA!”, but alas, we have lost them!  O’well, maybe I will be around in 5 years and in 2015 I will update this list again.

 

References:

1.      “Integrated Module Board”, Imbera Website, www.imbera.biz

2.      Holden, H.T. & Carrier, P., “Power Integrity Effects of High Density Interconnect (HDI)”, DesignCon-2009, Feb. 2009

3.      Holden, Happy, Chapter 5-HDI Materials, “HDI HANDBOOK”, Version 1.0, pcb007-2009, free PDF download at http://hdihandbook.com

 

 

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EIGHT (8) KEY HDI DESIGN FEATURES

June 26th, 2010, by | Permalink | No Comments

 Now that I am retired and working on PCB Fabrication Projects here in Taiwan, I have collected some of my HDI design strategies and condensed them down into 8 KEY DESIGN FEATURES.  Let me list them now before I forget them:

  1.      Where to place the blind vias
  2.      BGA Breakout
  3.     Reduction of the BIG drilled vias (GND/PWR)
  4.       Automation of Routing – Incremental execution
  5.     Horizontal-Vertical microvia routing pair
  6.      Finer traces/spaces and vias/pads
  7.      BC and decoupling capacitor removal
  8.      Split PWR plane supply with blind-vias

 WHAT DENSITY ARE YOU GETTING?

Before I explain these 8 design features, let me ask, “What design density are you getting now”?  A ‘high-density’ board usually has between 90 to 140 connections per square inch (that is, the total connections (pins) on both sides of a board divided by the length X width of the board) while and HDI board can have from 130 to 650 ave. connections per sq. inch.  If you look at the inner-layers (I/L) of this board, you see the following:

  • §         Typical through-hole boards get from 2.6 to 6.8 inches length per square inch area.
  • §         Users are now reporting getting 15 to 21 inches per square inch routing on HDI layers, a 3X to 4X improvement.
  • §         Far side HDI routing is 10 to 14 inches per square per layer.
  • §         This is going from 6-8% routing efficiency to 20-28% routing efficiency.

1. Where To Place The Blind Vias

Blind-vias have historically been placed around the perimeter of devices including BGAs.  This is usually the best place for them until the pin count begins to exceed 200 pins, after that, placing the blind-vias to form channels is a much better strategy to increase density.  This is seen in Figure 1.

Figure 1: Blind vias are more effective under BGAs in 'Channels'.

Figure 1: Blind vias are more effective under BGAs if placed into ‘Channels’.

 2. BGA Breakout

The new technique of “swing-fanout” developed by Charles Pfeil of Mentor Graphics [1] is one of the most important techniques to open up multiple channels for BGA breakout.  We call this “the Boulevard Breakout” because, like a freeway, there is multiple channels opened up to now route the breakout traces.  This alone will reduce the maximum layers by 2 to 4 layers minimum or even more.  This technique is seen in figure 2 and in Charles’s Book. [1] [2]

Figure 2

 Figure 2: Above ~200 pins, the BGA Breakout can be improved by using the “Swing-Via Approach” developed by Charles Pfeil of Mentor. [1], [2]

3. Reduction of the BIG Drilled Vias (GND/PWR)

The third technique is to reduce the number of drill vias on the board.  The easiest way to do that is to consider the stackup.  What are the most numerous vias on a board?  ANS: “The vias to ground.”  So if the ground layers that is typically LAYER-2 were moved to the surface-then you do not need vias to connect the component to ground, just a ‘tie-in’.  This can eliminate MAY large vias and by the same token, “what is the second most numerous vias on a board?”  ANS:  “The vias to power.”  So if power is moved from the center of the board to be LAYER-2, a blind-via can replace the larger TH via.  Again with the larger drilled vias being eliminated.  By eliminating 20% to 40% of the larger drilled TH vias or drilled buried vias, there is now sslide42pace on the I/L for 2X to 3X more traces.  These alternatives can be seen in Figure 3.

  •           Use of Microvias in Place of Through-Holes
  •           Layer Stackup Changes to Eliminate Drilled Holes
  •           Using the Blind Vias to Form Channels
  •           Placing the Blind Vias to Open Up Boulevards

 

 

 

 

 

 

 

 

 

 

 

Figure 3: Alternative stackups and replacing TH with blind-vias can help reduce layers.

 4. Automation of Routing – Incremental Execution

Significant improvements have been made to PCB auto-routers in the last few years.   Yet, they will never replace a skilled design person that has years of experience.  The problem is ‘getting years of experience’ or ‘having the time to implement your experience’!  This is where your experience came come to your rescue!  Today it is possible to “automate your hand routing skills” using the new ‘flexible’ auto-routers.  By annotating nets by their electrical performance, and ‘incrementally’ routing these selected nets to particular layers in the stack-up, using SI and PI driven routing, you can create the “AUTO” equivalent of precision hand routing.  Like the Figure 4 below, select ‘one’ net and autoroute it, tune it and then do a SI / PI simulation on it.  Capture the performance and save in the “CONSTAINT” part of the design tool.  Now autoroute all the nets in this performance class using the “CONSTRAINT” to guide it and assigning it to specific layers. This is repeated until all the nets are routed.  By storing the ‘Procedure’, the next time it can be used just by calling it back.  This type of automation is needed as board become more complex with more nets and more-fine pitch components.

slide31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5. Horizontal-Vertical Microvia Routing Pair

An important part of ‘No. 4 design strategy’ is the have an adjacent layer-pair for routing that uses only a blind-via for the crossover.  These can be seen in Figure 3 above as the ‘second’ tier of diagrams.  Each Type of HDI has a blind-via for the routing crossover from ‘horizontal’ to ‘vertical’. These structures can be created by skip vias, multiple build-up or sequentially laminated drilled and laminated vias.  This is also a via structure you will want to have because it provides routing of high-speed critical nets using only the cross-over from horizontal to vertical of small low-inductance blind vias.  These are the lowest inductance vias in the board and ideal for the highest-speed nets.  These will also have a very high density because the crossover will be small blind vias, not the larger buried or TH vias.

 6. Finer Traces/Spaces and Vias/Pads

An important part of increasing circuit density on PCBs is using finer traces/spaces along with smaller vias and pads on those vias.  Work closely with your PCB fabricator to utilize the ever-changing circuit fabrication capability within the industry.  Typical ROADMAPS or evolutionary changes in fabrication capability are listed here:

  •  Denser Inner Layers (traces/spaces)
  •                          –        .004”/.004” to .003”/.004” to .003”/.003”
  •  Denser Build-up Layer (via / lands)
  •                        –        .006” / .014” to .004” / .012” to .004” / .010”
  • Smaller Drilled Holes (via / lands)
  •                      –        .012” / .024” to .010” / .020” to .008” / .018

7. BC and Decoupling Capacitor Removal

With faster rise-time devices and lower power supply voltages, comes the need for lower power distribution networks impedances.  At high frequencies, this can only be achieved by reducing the distance between PWR and GND.  We have called this ‘buried capacitance’ (BC) but ‘distributed capacitance’ might be a better name.  Starting at 0.005” to 0.004” between PWR / GND, there is a lowering of the PDN impedance.  0.003” is the lowest cost FR-4 that can be used, as below 0.003”, the materials start to get very expensive, quickly.  But as they get thinner, and with higher Dk dielectrics, an increasing capacitance is created between the PWR/GND.  Enough that it is practical (and essential) to start to remove SMT decoupling capacitors.  Using the Reference Cited [4], up to 80% of the normal SMT decoupling capacitors can be removed, freeing up additional room for routing and components.

8. Split PWR Plane Supply with Blind-vias

The last technique involves a design feature used primarily in IC design.  That is to use two, orthogonal layers to distribute PWR as a ‘Mesh Structure’ and to place signals between the different voltages.  This can be seen in Figure 5 and the structure is called a ‘Dual Offset Coplanar Stripline w/Separate GND Reference’.  Line widths and dielectric distances are given for the various impedances that are commonly used.  This structure has the advantage of lower crosstalk but more importantly, it provides voltage to all the components from ‘LAYER_2’ and LAYER_N-1’ using only a blind-via.  Again, helping out with ‘Rule No. 3 design strategy’.

slide51

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

With these eight design techniques, you should be able to achieve 3X to 4X routing density while also reducing your overall design time.

 Good Luck

 Additional details and illustrations are available from my HDI HANDBOOK. [4]

REFERENCES

  1. 1.      Pfeil, Charles, “BGA Breakouts & Routing”, Version 1.5, Mentor Graphics-2008, www.mentor.com
  2. 2.      Pfeil, Charles, “Routing BGA Fanout Patterns by PCB Region”, Printed Circuit Design & Fab, July 2008 pp. 47-48
  3. 3.      Holden, H.T. & Carrier, P., “Power Integrity Effects of High Density Interconnect (HDI)”, DesignCon-2009, Feb. 2009
  4. 4.   Holden, Happy, “HDI HANDBOOK”, Version 1.0, pcb007-2009, free PDF download at http://hdihandbook.com

 

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“Made In America”

June 26th, 2010, by | Permalink | No Comments

made-in-america

 

 

 

 

 

 

 

“Manufacturing has long been viewed as an essential pillar of a powerful economy. It generates millions of well-paid jobs for those with only a high school education, a huge segment of the population. No other sector contributes more to the nation’s overall productivity, economists say. And as manufacturing weakens, the country becomes ever more dependent on imports of merchandise, computers, machinery and the like — running up a trade deficit that in time could undermine the dollar and the nation’s capacity to sustain so many imports.” By LOUIS UCHITELLE, Published in the New York Times on July 20, 2009

THE SIX ENDEMIC WEAKNESSES

This was part of an article about the closing of a 57-year-old family printed circuit manufacturing business (Bartlett Manufacturing) in Cary, IL.  This reminded me of an article by MIT published nearly two decade ago (1990) after an MIT Commission looked into the loss of industrial performance in the US compared to Japan.[#]  The commission spent a year and a half conducting 600 interviews on three continents.  The Report exploded the view that “It’s a Government problem”, instead, it found six endemic weaknesses in the US:

1.      The first weakness was found to be the out-dated strategies, most notably mass production.  The pattern of production we cling to is that gigantic wheel with cogs that must keep turning no matter what, to produce large numbers of undifferentiated goods.  The workers are highly specialized and the relationship between manufacturers and suppliers is distant, adversarial and litigation-bound.  Compare that to the modern system of “lean” production, which is smaller, more nimble and can change models without shutting down the plant.  This produces a diversified set of products tailored to individuals, and tailored to a ‘broadly’ trained workforce that has flexibility to adjust quickly.  The landscape of mass closing of GM and Chrysler plants in the US and Canada attest to the ‘failure’ of this old manufacturing philosophy. 

In the same vein is our parochialism to believe that everything worthwhile lies within the USA.  This blinds us to ‘better technologies’.

2.      The second weakness was short time horizons.  Consider our electronics industry.  After WWII we were producing 96 percent of the consumer electronics we use; today we produce less than 2 percent of the consumer electronics we use.  The commission called this “not sticking to our knitting.”  There is a ‘mis-calculation’ of Return on Investment, where jobs and taxes are ignored.  Part of this short-term orientation is the high cost of capital – - maybe 50 percent to 100 percent higher than in China.   Financial ‘tools’ play to high a role in consuming available capital and the ‘quick profit’ to heady a reinforcer in our short-term horizons.  The commission cited seven factors besides the high cost of capital, which are responsible.

3.      The third weakness was the technology difficulties in going from invention to product.  The US invented transistors, color television, the VCR and mobile phone. Yet only a trickle of these products is made here today.  Of the products we do make, many have defects.  Our automobiles now have 30 percent more defects in the first six months after they are sold than Japanese automobiles, or Japanese / Korean automobiles build here in the USA.  Two-thirds of our industrial R&D funds go toward inventions while one-third goes toward the processes of making these products.  Our foreign competitors reverse the numbers.  Maybe we have forgotten Juran and Deming, but inventing only starts the cycle of “Continuous Improvement”.  Our old adage, “if it ain’t broke, don’t fix it” hardly will achieve daily, relentless, gradual improvement.  We favor the inventor and think a career in manufacturing spells drudgery, while the Asians see manufacturing as an opportunity to ‘create the next, better product”.

4.      The fourth weakness was the neglect of our human resources. We pioneered mass education, but today we rank between 15th and 18th in high school literacy and numeracy.  This is happening at the worst possible time – when we need our work force to be able to read and understand more complex manuals of instruction.  On-the-job training is also inadequate.  Between $50 billion and $150 billion a year is spent on on-the-job training that goes primarily to teach people the basic functions the high school didn’t teach them.  Whatever is left is used to create specialists rather than making them capable in a broad sense to be flexible at their work.

5.      The fifth was a failure of cooperation.  Our companies have large, deep hierarchical organizational structures (sometimes twelve layers deep), while other newer companies use a much shallower structure maybe three layers deep.  This shortens feedback between designers and makers by 2X.  This pattern is repeated by large numbers of suppliers whom we deal with like adversaries instead of having a few suppliers treated as partners in a common effort.  Some of this might stem from the current trend to ‘overpay’ CEOs, where the current ratio between hourly worker and CEO compensation is 400X and being reworded by Boards to layoff workers rather than fixing product development or manufacturing efficiency and quality.

6.      The sixth and last weakness has to do with government.  When they started the study, they were told the government was to blame for everything, that was not the case.  They did find that the U.S. government and U.S. industry functioning as two totally independent entities, each oblivious to the other’s aspirations, needs goals, and purposes.  The CRATR Program was intended for individuals and companies to take advantage of US Gov’t Laboratories, but that is not achieving its goals.  Foreign governments have their laboratories actively involved in creating business opportunities and IP that will enhance their businesses and create jobs.

 

The MIT Commission identified three trends in this nations industrial performance for the early part of the 21st century: First, we will be going more international.  The ownership, the location of the company, and the technologies it uses, will all be international.  Second, people will expect more sophisticated products.

Third, technology will play an even more important role tomorrow. 

They identified three technologies as dominant in the 21st century: information sciences, life sciences including biotechnology, and material sciences and technologies.

Finally, the MIT Commission took the six weaknesses, the three trends, and the best practices patterns they observed all over-the-world, and produced five imperatives, which, if pursued by government, industry and the educational institutions of this nation, will give us back our productive edge.

THE FIVE IMPERATIVES

·                The first imperative is to focus on producing well the new ways.  By this they meant putting production ahead of finance.  Finance is important, but a CEO MUST understand his products and the production processes it employs.  “LEAN’ concepts need to be adopted and supported (you can download a free E-book on LEAN Mfg. Concepts from http://hdihandbook.com).  Managers need to become very knowledgeable of their products, their competitors, and their core competencies.  Boards need to embrace more than “compensation” and focus on the products the company produces and those production means.

·                The second imperative is to cultivate a new economic citizenship.  We must stop viewing the workforce as a cost-factor to be minimized, and start to regard it as a precious asset to be nurtured and cultivated.  Flexible manufacturing and flexible products need flexible workers.  Responsible workers involved in doing so much more must be rewarded more with the profits of the company-and this is what the best companies in the world do.

·                The third imperative is to blend cooperation and individualism.  In professional sports, the most successful teams have a blend of individualism and cooperation.  When you combine the American tradition of cooperation with our individualism, the results will be stronger than either.

·                The fourth imperative is for us to learn to live in a world economy.  We must learn foreign languages, cultures, practices and especially, technologies.  That means benchmarking our products and services against the best internationally, not the company next door or in the next state.  We also must insist that our goods are treated as fairly abroad as foreign goods are treated here.

·                The fifth and final imperative is to provide for the future, to invest in the broadest sense for the education of our children.  We must insist on educating our children in the best way possible.  I had the advantages of the “Sputnik Scare” and “the missile gap” creating new emphasis on science and math when I was going to school.  The result, “landing on the moon in this decade-1969”.

 

“The imperatives presented by the MIT Commission are not a menu from which to pick a favorite.  They must all be used effectively to regain our international competitiveness.  There are no shortcuts!” [#]

 

 

“One tactic for strengthening the manufacturing sector, in the administration’s view, would be a shift in tax policy. The research and development tax credit, which is now subject to renewal by Congress, would be made permanent, encouraging much more R. & D. among manufacturers, a senior Commerce Department official argued. And foreign taxes paid on profits earned overseas would not be deductible in this country until the profits were repatriated, a restriction that might discourage locating factories abroad,” wrote Uchitelle.  The goal is to arrest manufacturing’s dizzying decline. It “was the pillar on which we built the middle class,” said Thea Lee, policy director for the A.F.L.-C.I.O., “and it is hard to see how you rebuild the middle class without reviving manufacturing.”

 

Finally, it would not be right to let the whole Apollo moon landing 40th anniversary go by without a comment, right? After all, everyone else has an opinion on what it meant and what it means. So please indulge me, here’s my take:

I am NOT going to go over what an accomplishment it was, what it taught us technically, what it taught us about what we can do with a major commitment (people, money, priorities). Many others have covered that.

But here’s my dilemma: as someone who has read and owns many books and seen documentaries on the Apollo project, and admires it beyond mere words, I am nevertheless troubled by all this anniversary-celebration business.

Here’s why: too much celebrating of the past means that the engineering accomplishments of the present are taken for granted. It’s almost as if the Apollo celebration has that “yes, those were the days” atmosphere. Back then, engineers and astronauts were honored and respected by society; today, it’s another story.

# This was from a talk given by Michael L. Dertouzos on March 30, 1991 before the Commonwealth Club in San Francisco.

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Process Automation: Various Ways To Automate

June 26th, 2010, by | Permalink | No Comments

One of my favorite topics is process automation.  This comes from it being my first job at Hewlett-Packard in printed circuit manufacturing.  I had no background in plating or wet processes, but my chemical engineering had prepared me for process automation – - and my computer process control specialization was just ‘itching’ to look for an application.  Fortunately, in 1971, H-P developed the hp-35 scientific calculator and we were unprepared for the deluge in orders for the unit.  Marketing had told us we would be lucky to sell 3000 a month of the $395 machine, and instead, orders were pouring in at a rate of 3000 per hour!  With a special welded-gold keyboard, silver-plated COB display and an 8-layer multilayer logic board, we were desperate for more printed circuits.  There was not a lot of merchant capacity for PCBs in those days so I got my chance to ‘automate production” by a factor of 500X.

Process Automation

In reviewing the options of higher productivity for plating and wet processes, I became educated on ‘process automation’.  My basic machine choices were 10:

·         Vertical or horizontal conveyorized transport (Figure 1a)

·         Overhead conveyor or powered roller (Figure 1b)

·         Walking beam or I-beam transport (Figure 1c)

·         Split-rail pusher or side-arm return type transporters (Figure 1d)

·         Cantilevered  or overhead (gantry) programmed hoists (Figure 1e)

 We selected the horizontal conveyorized machines for etching, developing and stripping and the cantilevered programmed hoists for electroless copper, black oxide and smear removal with multiple overhead programmed hoist for electroplating.  You can see that first computer controlled system in Ref [1] and [2].

fig_1a1fig1c

 

 

 

 

 

 

 

 

 

FIGURE 1a: Vertical and horizontal processing lines   FIGURE 1b:  Overhead and powered-roller conveyorized lines

Low Cost Automatic Transporter

In 1975, one of our 9 prototype facilities developed their own low cost automatic panel transporter.  Figure 2 shows the electroless copper processing line built over the manual tanks.  This transporter and frame costs only about $7000 to manufacture.  It is simple enough for any PCB maintenance personal to construct.  The frame is 2.0 inch painted tubular steel welded together and the transporter is constructed out of high-strength aluminum tubing that has been painted.  Detailed construction drawing will be available in the Second Edition of my HDI HANDBOOK [3], available Jan. 5, 2010.  The handbook can be downloaded now free from my BLOG at:

              http:// communities.mentor.com/mgcx/community/pcb/pcb_blogs/happy_holden

fig_1b2

FIGURE 1c: Overhead walking-beam and cable transportation systems  fig1d FIGURE 1d:  Side-arm and split-rail pusher type cantilevered return systems

 fig1e

 

 

 

 

 

 

FIGURE 1e: Cantilevered and gantry (overhead) hoist systems   

The system in Figure 2 has two additional transporters running on it.  Each transporter is battery powered and runs autonomously.  The controls for the system are very simple and basically they are electromechanical, so again, any PCB maintenance personal can construct and maintain them.  The transporters are controlled by a timer at each process step.  Once the transporter arrives on station, it starts the timer for that process, when the timer ‘times-out’, the load is lifted and the transporter moves to the next process step.  After unloaded at the end, the transporter is reversed and moved back to the load station by an operator.  The slightly larger electroplating process line transporter was arranged in an oval, with the ‘load’ adjacent to the ‘unload’.

fig2

 

 

 

 

 

 

 

 

Transporter Details

The seven sketches in Figure 3 provide an overview of how simple this transporter and frame is to build.  Each additional transporter is only about $3000.  Being battery powered, there are no high voltages involved, nor is there any electronics or computers.  It is just a simple, rugged, reliable robotic transport system.  Let’s start the descriptions:

 

 

 

Figure 3a shows the simple transporter drive arrangement.  A 12V D.C. motor (with self actuated brake unit- A) drives the transporter forward by a chain drive attached to two drive shafts.  These are the drive wheels that run on top of the 4.0 x 2.0 inch square

fig3a

steel channel.  There are two top guide wheels and one bottom guide wheel that keep everything aligned.  This entire assembly is behind the process tanks, housed in a plastic shroud, so that no debris can fall into any of the processes.

 

 

 

 

Figure 3b is details on the transporters lift mechanism.  The 12V D.C. motor (B) provides lift and drop for the PCB load.  The lifting bar is guided and pulled up by a stainless steel cable that winds on a drum connected to the motor.  On the cable is a bobbin that contacts a micro-switch at full lift to kill power to the lift.  Dropping is provided by gravity and the motor running in reverse until the ‘drop’ micro-switch is closed.

 Figure 3c provides a close-up of the frame and track for the transporter.  The frame is 2 inch diameter mild steel pipe and it supports the two 4 inch x 2 inch steel channels on which the transporter wheels drive the transporter forwafig3brd.  The fixed timing control box is also illustrated and how it aligns with the transporter.

 

 

 

 FIGURE 3b:  Transporter-Lift

 

 

 

 

 

Figure 3d is a close-up of the fixed timing control box for each process tank.  It consists of an electronic or electromechanical timer, an electromagnet and a magnetic reed-switch (A).  On the transporter is a permanent magnet and a magnetic reed-switch (B).   The control sequence is illustrated in Figure 3f and by the control diagram in Figure 3g.

fig3c

 

 

FIGURE 3c: Frame details        FIGURE 3d: Close-up of control system box for each process

 

 

 

 

 

 

 

 

 

 

Figure 3e is the manual transporter control box mounted on each transporter.  It shows the condition of the charge of the battery and has manual switches to raise and lower the load as well as to move the transporter in reverse back to its ‘load’ station.

 

 

FIGURE 3e: Control- Box               FIGURE 3f: Control- system, running sequence

 

 

Figure 3f shows the typical operation of the transporter in its “Automatic” mode: 1. When the transporter first starts down the frame and encounters the first process tank, the permanent magnet on the transporter will close reed-switch A in the fixed control box.  2.  This indicates the transporter is “On-Station” by activating the electromagnet that in turn closes reed-switch B in the transporter and it stops.  Also, the process timer will start and the transporter will lower its load until its “drop” micro-switch is closed.  This will stop the drop motor.   3.  When the process timer times-out, it will cancel the electromagnet and the transporter will lift the load until the “lift” micro-switch is closed.  4. At the top of the lift, when the “lift” switch is closed, a delay timer allows for ‘drip-off’ and then the transporter moves forward the cycle repeats itself at the next process control box (repeat 1) until the unload station is approached and its proximity switch (A) is activated by the permanent magnet, which turns on the electromagnet and the transporter stops and an alarm sounds as it lowers it load.  Later the operator will manually bring the transporters back to their loading position.

 

Figure 3g is the simple electrical diagram for the system.  It shows the simple fixed process station control box with the timer; electromagnet and proximity switch A and the transporter controller along with its manual control box.  The transporter needs only the proximity switch B, upper and lower limit-switches, two drive motors and two manual move switches.

 

FIGURE 3g: Control system- electrical diagram              

Finally

This simple process automation transporter is both simple and inexpensive.  It is well within the skills of most maintenance personal for a small proto or quick-turn PCB facility.  As such, it represents a major step in throughput automation and productivity.  It is compatible with manual operations and does not interfere with the normal use and maintenance of those processes.  The logical next step after implementing ‘process automation’ is ‘automatic process control’.  There is also a new chapter in the Second Edition of the HDI HANDBOOK on that topic as well. 

                                   I hope you can use this little bit of automation!

 

REFERENCES

1.      “Plating Automation Comes to Printed Circuits” by HHolden, Plating and Surface Finishing, Oct. 1974

2.      “Justifying Process Automation” by HHolden, NEPCON, 1972

 “HDI HANDBOOK”, written and edited by HHolden, 631 pages, pcb007 publisher, Jan, 2009, available at http://communities.mentor.com/mgcx/community/pcb/pcb_blogs/happy_holden

 

 

 

 

FIGURE 2: Battery powered independent transporters for PCB panels built over manual processing tanks.

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New Chapters for the HDI HANDBOOK

June 26th, 2009, by | Permalink | No Comments

Hopefully, you have taken the opportunity to download my free E-book, the HDI HANDBOOK. NOW is your chance to tell me what would make interesting reading for FUTURE chapters in the SECOND EDITION of the HDI Handbook.  Here are some brief descriptions of what I am planning to add now.  But this book isn’t for me – it’s for ALL of you!  So provide me with some advice and if you know the perfect expert that could write that chapter, throw that in as well.  I thank you all now for helping me.  The Second Edition will be available for download the latter part of 2010.

1. Automatic Chemical Process Monitoring and ControlHigh-speed PCB and FPC manufacturing with increasing density requires better chemical control of processes.  This chapter will describe traditional instrumental and some not-so-standard methods of automatic chemical analysis and control.  The PCB processes, individual anion and cations and other indicators are highlighted for control.

 

2. Process Automation Strategies and EquipmentComplementing high-speed manufacturing is high-speed automated equipment.  This is the first time that 10 different types of automated PCB equipemnt has been described and features.  Conveyorized: horizontal, vertical, overhead and hybrid;  Process Tanks: walking beam, cable, split-rail pusher and side-arm return-type;  Programmed Hoists: cantelevered and gantry.  Control systems, programming hoists, simplified control theory and automation strategies are also described.
3. Application Examples of Design of Experiments- Dr. Sam Shina of UofM-Lowell, has prepared some advanced topics in the applications of DoE.  Sam was a printed circuit fab process engineer and assembly engineer at Hewlett-Packard before going back to school to get his PhD.  Dr. Shina is a professor of Mechanical Engineering and specializes in DFM, reliability and Design strategies. 

 

4. Impedance, Stackups and CrosstalkA complete look at signal tracts to transfer signal power from one device to another by consideration of materials, stackups, impedance matching and crosstalk.  The various high-speed models for microstrips and stripline, of differential signalling, with coplanar and waveguide alternatives are explained.  Advanced noise explanation of crostalk are also explained.

 

 

 

5. BGA Breakout StrategiesCharles Pfeil of Mentor has agreed to write a chapter that summarizes his theories and book on ” BGA Breakout and Routing-ED II”.  His new technique for breakout of large BGAs has revolutionised the wiring of boards.  It was highlighter in Chapter 3, but in only 4 pages- now it will be explained in a lot more detail.

 

 

6. Coupons and Techniques for Process ControlRon Rhodes had a distinguished carreer at Bell Labs and will provide a chapter on the use of PCB coupons to highlight  quality and process capability.  Reliability is another set of coupons and have a different focus.  How to interpret and “what these coupons mean” is another distinguished topics that Ron created by writing a column in CircuiTree magazine from 1994 to 2007.

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HDI Training for Fabricators

June 15th, 2009, by | Permalink | No Comments


I’m sure all of you are aware of the rapid progression of HDI technology used in mobile phones, telecom and advanced consumer products.  But HDI is rapidly being introduced into military and space programs as well.  The HDI for military and space has to be ultra-reliable and capable of harsh environments.  The cost to develop these materials and fabrication processes can be quite high.  So the IPC has teamed up with the U.S. Navy and the NSWC-CRANE state-of-the-art PCB facility to develop an advanced HDI Hands-On fabrication course this fall (PD-05).

Open to all fabricators, this is a 3-day, hands-on, working course that embraces the latest advanced HDI features required by new military and aerospace programs and employed by advanced telecom systems as well.  The October 13-15 working laboratory event is proceeded by 5 2-hour WebEx classroom instructions on Sept. 14-18, to provide more “hands-on” time in Oct.  The “Hands-on” attendance is limited to only 21 participants, due to the nature that everyone will build HDI boards, so register early at the IPC.  http://www.ipc.org

PD-05: High Density Interconnect

October 13-15, 2009 – Crane, Indiana

This HDI fabrication hands-on workshop provides an essential instructive platform for companies interested in learning the advanced fabrication processes of HDI technology. Attendees will be provided a “hands-on” working laboratory event that features informative technical tutorials and an invaluable “hands-on” workshop, where you will actually build these HDI structures.  You will be provided the instructional HDI technology as it relates to advanced HDI fabrication — as needed by numerous aerospace, military, telecom and computer OEMs with an emphasis on high reliability and endurance. Join us for this enlightening series, and discover what you need to know to implement HDI technology in all of its forms.

What You Will Learn:


Tutorial presentations and hands-on exercises cover these topics :

  • Imaging and etching — achieving fine lines and spaces, controlled copper etch
  • Lamination & Via formation — mechanical and laser drilling & lamination of new materials
  • Metallization & Electrodeposition — desmear, electroless copper, direct metalization and semi-additive processing— improved throwing power copper fill, enhancing through hole and microvia reliability, copper thickness requirements for thermal reliability and process controls
  • Process control coupons, DOE, Reliability and testing—in-process coupons for HDI and reliability coupons
  • HDI Exercises at NSWC-Crane Laboratory
  • Fine line Direct Imaging/etching- 25 um traces/25 um spaces (~1 mil lines/spaces) using new sacrificial super-foil “DFF”
  • Lamination of new thin Laser Drillable Prepreg, like 1086LD or 1067LD for power integrity and impedance control
  • Copper “Super-fill” plating to plate up microvias from 75~150 um in diameter
  • Drilled via filling with epoxy to plug buried vias
  • Etching & laser drilling ceramic BC materials for buried capacitors and distributed capacitance
  • HDI process control coupons to monitor the HDI fab process
  • IST coupons to test the reliability of the finished HDI board.

High Density Interconnect Webcast Series

September 14-18, 2009

(10:00 am – 12:00 am Central Daylight Savings Time)

This series of five two (2)-hour webcasts will address key technologies for fabricators who want to get into advanced HDI fabrication.

September 14, 2009 – Overview/ Design/ Process Control & Reliability

  • Process control coupons, DOE, Reliability and testing—in-process coupons for HDI and reliability coupons

    • HDI Exercises at NSWC-Crane Laboratory
    • HDI process control coupons to monitor the HDI fab process

    • IST coupons to test the reliability of the finished HDI board

September 15, 2009 – Fine-line and Via-Formation

Imaging and etching — achieving fine lines and spaces, controlled copper etch

  • Lamination & Via formation — mechanical and laser drilling & lamination of new materials
  • Fine line Direct Imaging/etching- 25 um traces/25 um spaces (~1 mil lines/spaces) using new sacrificial super-foil “DFF”
  • Semi-additive processing (SAP) using new molecular interface technology to achieve 25 micron traces and spaces
  • Etching & laser drilling ceramic BC materials for buried capacitors and distributed capacitance

September 16, 2009 – Material Control and Lamination

  • Lamination of new thin Laser Drillable Prepreg, like 1086LD or 1067LD for power integrity and impedance control

September 17, 2009 – Via-Fill

  • Drilled via filling with epoxy to plug buried vias
  • Copper “Super-fill” plating to plate up microvias from 75~150 um in diameter

September 18, 2009 – Metallization & Electrodeposition

    • Metallization & Electrodeposition — desmear, electroless copper, direct metalization and semi-additive processing— improved throwing power copper fill, enhancing through hole and microvia reliability, copper thickness requirements for thermal reliability and process controls
    conference1jpg

    fabrication site

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Self-Learning Educational Opportunities for Designers

June 9th, 2009, by | Permalink | No Comments

Improving your personal performance is a large topic. But a critical area is high-frequency electrical performance for the board in both signals and plane PDN. Other new trends are incremental design/validation methodologies and the improved use of constraint-autorouting, as well as re-use of circuits and DfT.  More on this in future BLOGS.

Here is where I suggest that you start looking for where you can learn these new topics. First, if you have not downloaded my new HDI HANDBOOK, this is a good place to start. The 631 page e-Book is FREE, so there is no excuse not to have it. My Chapter-4 “HDI Electrical Performance” is written by Dr. Eric Bogatin, and Dr. Bogatin has many more resources available for learning. His past Web Series on “No MYTHS Allowed” can be downloaded from www.gigatest.com/Publications/PubsIndex.jsp This site has 105 documents, lectures and tutorials available from Dr. Bogatin. Figure 1 shows a typical slide form one of his lectures. Dr. Bogatin’s current Internet Site is http://www.BeTheSignal.com and it also has many free tutorials on it .

Bogatinsample

Bogatinsample

Another very useful design ‘Toolkit’ is provided by Kenneth Wood, owner of Saturn PCB Design in Deltona, FL.[3] His Toolkit is shown in Figure 2 and provides software to calculate physical and electrical characteristics of vias and conductors; signal bandwidth and max. lengths; differential-pair impedances; padstack designs; drill/wire gauge conversions; min conductor spacing for voltages; and microstrip/stripline impedances. This can be downloaded at: (http://www.saturnpcb.com )

interface

interface

Another source of training and learning is to use Google and Yahoo to search the Internet for college classes in signal integrity, EMI Compliance, Design for Manufacturing or high-speed design. One such search yielded the “EE166: High-Speed PCB Design” course at Harvey Mudd College in Claremont, CA. HMC has the distinction of being awarded “One of the Top Undergraduate Engineering Schools in the US”. In this case it was the lecture notes and labs by Prof. Sarah Harris   -(www3.hmc.edu/~sharris/class/e166/)[4].

The IPC Designers Council and the IEEE are constantly running courses for designers.

Last, to reduce schedules is one of “Push Left”, “Do it right the first time” and distribute more activities in parallel. Move critical activities and checks/audits up earlier in the design process. Find any problems or mistakes early. IF [errors] found in manufacturing, critical schedules and costs are bound to be impacted. Now is the time to “learn to use the autorouter correctly” and “how to apply signal and power integrity”!

Finally, if you are “surplused”, “made redundant”, “sacked”, “displaced”, “sacrificed” or just “let GO”, Mentor has the “Displaced Worker Program”. [5] You may take Mentor classes on a “Space Available” basis, for free, and that includes online courses as well as in-class courses in Austin, Boston (Marlborough, MA), Chicago, Minneapolis, Dallas, Denver (Longmont, CO), Portland (Wilsonville, OR) and San Jose. Go to http://www.mentor.com/training_and_services/training/dwp to check on availability.

REFERENCES

1. HDI Handbook and other tech papers, tutorials at http://communities.mentor.com/mgcx/community/pcb/pcb_blogs/happy_holden

2. Eric Bogatin’s “No MYTHS Allowed” at GigaTest Labs, there is 105 doc. www.gigatest.com/Publications/PubsIndex.jsp & www.bethesignal.com

3. Free PCB Tools (www.saturnpcb.com) –vias, conductors, signals, diff pairs, padstacks, min. conductor Spacing & impedance.

4. University course lectures (like EE166 High Speed PCB Design by Dr. Sarah Harris of Harvey Mudd College-(www3.hmc.edu/~sharris/class/e166/)

5. If ‘out of work’, Mentor has the “Displaced Workers Program” allows you to audit our training for free, go to http://www.mentor.com/training_and_services/training/dwp

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Buried Capacitance Materials for Power Integrity

May 27th, 2009, by | Permalink | No Comments

For everyone using the new HyperLynx PI tool, here is a list of available PCB Laminates that are candidates for the PWR/GND pair in your stackup.  This table is from page 217 (Fig 32) of my HDI HANDBOOK.   The entire Chapter 5 is about “Materials for HDI” and you might find it interesting.

Some of the abbreviation used in the Table are: CCL=copper clad laminate; film=copper clad unreinforced polyimide film; Prepreg=epoxy fiber-glass coated b-stage material for lamination; RCF=resin coated copper foil; Sequential lam=the material requires some processing (one side etched) and lamination before it can be used; Both sides etching=the copper for PWR and GND can be etched and then the material laminated in to the stackup.

materials4


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Free Download ! All You Wanted To Know About HDI….and MORE!

May 19th, 2009, by | Permalink | No Comments

The HDI Handbook – A comprehensive high-density interconnection resource for designers, fabricators and assemblers

First Edition, Written by Happy Holden, et al., Edited by Happy Holden and Diane Neer Here is the link to DOWNLOAD the HANDBOOK (53 MB ZIP)

I have finally finished my book on high density interconnects (HDI). Along with the help of 9 friends and fellow PCB experts, we have created a 631 pages book about HDI.

FOCUS: This book is not intended to introduce PCB Technology to the reader, that is effectively done by Coomb’s PCB Handbook. It does take up High Density Interconnects (HDI) and microvias in much more detail than where Coomb’s left off.

The 16 chapters cover:

Section 1: Introduction

The widespread use of new electronic components employing Ball-Grid Array (BGA), Chip Scale Packaging (CSP), and other evolving technology form-factors means new fabrication techniques must be used to create printed circuit boards (PCBs) that will accommodate parts with extremely tight lead pitches and small geometries. In addition, extremely fast signal rise-times and signal bandwidths challenge systems designers to find better ways to overcome the negative effects of inductance, noise, radio frequency interference (RFI) and electro-magnetic interference (EMI) have on their product’s performance. The use of PCBs incorporating microvia circuit interconnects is currently one of the most viable solutions on the market. Assemblies can be charted by their characteristics. The interaction of interconnect elements, such as assembly, PC boards, and components, are described by their metrics: assembly density, assembly complexity, component complexity and board density. –Happy Holden

Section 2: The Interconnect Market

HDI products, size and market growth rates, examples of different HDI products using the three Platforms: 1. Consumer and mobile phones, 2. substrates and 3. large-high performance boards. The “HDI Vintage Chart” with the three ‘basic’ characteristics of HDI architecture. -Karen Carpenter

Section 3: Design of Advanced Printed Circuits

As the electronic products industry continues to push the envelope of extreme miniaturization, product developments teams are being forced further into the realm of high density interconnect. Design techniques and substrates labeled exotic only a few short years ago are now considered mainstream. In particular, build-up substrate usage has grown dramatically, and is now found in a large percentage of high production electronic products. This Section is to educate and inform you on the technologies, needs, issues and solutions available today for advanced substrate design. The focus will briefly cover the 4 changes to TH PCB design techniques required for HDI and the IPC Design Standard 2226. -Happy Holden

Section 4: Electrical Performance

The good old days of 10 to 16 MHz clock frequencies are gone. It used to be the chief design challenge in circuit boards or packages was routing all the signals in two layers and getting packages that wouldn’t crack during assembly. The electrical properties of the interconnects were not important because they didn’t affect system performance. But the world has changed in the past 10 years. Clock frequencies on chip now are over 3 GHz, and on board, are over 800 MHz. In most systems, as the clock frequency goes up, the rise time always gets shorter. A shorter rise time means signal integrity problems increase dramatically. Signal integrity is broadly concerned with the problems that arise from how the electrical properties of the interconnects affect system performance. -Dr. Eric Bogatin

SECTION 5: Materials

Many new materials now support HDI. The material performance and slash-sheets from IPC HDI Material Standard 4104 explain many of these. -John Andresakis

SECTION 6: The HDI Mfg Processes

Various HDI mfg processes and structures are explained. These utilize standard PCB processes but with greater miniaturization and higher density. -Happy Holden

SECTION 7: Small Hole Creation

The machines, processes, quality concerns and issues with creating small vias. -Michael Carano

SECTION 8: Metallization

Desmear & metallization (electroless) ,including the materials and processes for paste in vias. -Michael Carano

SECTION 9: Fine-Line Imaging and Etching

Image transfer processes, stripping & etching fine lines, registration, equipment, and materials for fine-line image transfer. -Michael Carano from columns written by Dr. Karl Dietz

SECTION 10: Plating and Finishes

Plating, pulse-plating, small-holes plating and filling, final finishes. -Michael Carano

SECTION 11: Testing

AOI and electrical testing of HDI -Dr. Christophe Vaucher

SECTION 12: Quality, Acceptability & Reliability

Performance of HDI Benchmarking, Vendor readiness, qualification, quality issues, lab techniques and equipment. -Happy Holden

SECTION 13: Assembly Topics

Via-in-pad issues, fine-pitch, soldering & voids, in-circuit testing -Matt Wuensch & Mark Laing

SECTION 14: Embedded Components

Embedded Resistors, Embedded Capacitors, Distributed capacitance and Embedded Actives, the materials and design tools -Happy Holden

Section 15: Advanced HDI & Next Generation Technologies

The use of more complex components with very high I/O counts and increasing speed has pushed the interconnect into the realm of photonics and opto-electronics. The materials, processes and test vehicles for optical waveguides in printed circuits are reviewed. -Happy Holden

Section 16: HDI Substrates & Packages

This Section is to educate and inform on the technologies, design issues and solutions available today for advanced IC substrate design. The focus will briefly cover the challenges of wire bonding, flip chip, stacked dies and packages and through-silicon vias that allow various System-in-Packages (SiP) and 3D architectures. -Per Viklund

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