Fabless/Foundry Ecosystem Solutions

You’re creating chips with high functionality, multiple operating modes, low power consumption, and extreme reliability—pushing the manufacturing process to the limit. But your advanced ICs are increasingly sensitive to the smallest manufacturing variations, and that affects both performance and yield. Mentor's Foundry Solutions can help you solve your design challenges.

25 August, 2014

Sukharev_Valeriy_2013_02Are you stressed out over the effects of stress in your IC designs? Relaaaax…help is here!

A new publication on mechanical stress in ICs, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D, has just been released by AIP Publishing. Stress-Induced Phenomena and Reliability in 3D Microelectronics includes papers from international workshops held in the U.S., Germany, and Japan. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-ICs using through-silicon vias (TSVs). The potential stress-related impact of the 3D integration process on product reliability must be understood, and designers need solutions for identifying and managing stress effects.

The papers focus on Design-for-Reliability (DFR), and propose a stress management simulation flow that enables designers to model stress implications on their designs quantitatively. The papers also discuss multi-scale modelling and simulation, multi-scale materials parameters, and multi-scale analysis. Development of 3D-IC integration strategies provides a potential solution for overcoming the wiring limit imposed on interconnect density, performance, and power consumption of integrated circuits.

To order your copy of this AIP publication, click here. And chillax…stress is bad for people, too!

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18 August, 2014

Sawicki_Joseph_2014In a SPIE.TV interview, Joseph Sawicki, Vice-President and General Manager of the Design to Silicon division of Mentor Graphics, explains the challenges of moving from design abstraction to physical implementation to a successful yield.

“Design to silicon” is a complex process that continuously blends evolutionary trends, such as enhancements to 3D mask design and yield learning, with more revolutionary changes such as limiting the geometries and pattern options available to designers. How do we know what works? Design for test strategies insert circuitry into a design to enable us to determine if a device works properly after manufacturing. DFT helps fabless companies turn production designs into virtual test chips to help identify those “intersections” between the design and process that cause systematic issues. Armed with that knowledge, companies can then modify that issue out of the process and/or design flow.

Want to learn more about Mentor’s support for test and diagnosis? Click on the links below for more information…

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14 August, 2014

Design-style-based (systematic) defects are the major challenge to yield ramp at advanced process nodes, adding to the complexity of the basic process ramp. Because of its involvement in the design, manufacturing, and test, EDA is in a unique position to contribute toward the control, if not the solution, of this problem, through the use of automated pattern detection and analysis. Patterns can be useful throughout the entire flow, from design to verification to manufacturing to test. The goal is a pattern-aware EDA flow that minimizes risk, enhances manufacturing, and quickly finds issues when they occur.

In this pSawicki_Joseph_2014lenary presentation from the 2014 SPIE Advanced Lithography conference, Joseph Sawicki, Vice-President and General Manager of the Design to Silicon Division of Mentor Graphics, explores the many facets of pattern usage within the D2S process, and how pattern awareness can help resolve many of the challenges facing designers today.

For more information about Calibre pattern matching solutions, take a look at these additional resources:

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7 August, 2014

Failure analysis is a critical process in successful IC production. No matter how comprehensive the design rules are, no matter how thorough the verification strategies are, there will be chip failures in production. Understanding the cause of these failures is crucial to being able to implement design strategies and corrective technology to ensure the failures are eliminated in future designs. At its best, failure analysis enables design companies to adhere to the time-tested adage of inventors and designers everywhere—”Never make the same mistake twice.”

However, failure analysis has many layers. Layout-aware scan diagnosis can reduce the suspect area by up to 85% (compared to logic-only diagnosis), allowing engineers to focus on only those portions of a design most likely to contain the defect. With sets of diagnosis data, you can perform yield analysis to identify the most likely causes of yield failure, making volume diagnosis results actionable and drastically speeding up the analysis process.

Now there’s root cause deconvolution (RCD), a statistical technology that analyzes multiple layout-aware diagnosis reports to identify the underlying defect distribution (root cause distribution) that is most likely to explain a set of diagnosis results. RCD also enables “virtual failure analysis,” or the ability to determine defect distribution for a population of failing devices before any failure analysis is performed. With the ability to identify root cause of yield loss from fail data alone, RCD is a very cost-effective way of establishing a clear picture of the defect distribution before any failure analysis (FA) is done. This is something that has been virtually impossible for fabless companies, with little access to manufacturing data, to do in the past.

RCD-2By improving the failure analysis relevance and success rate, RCD can dramatically reduce the failure analysis cycle time from months to days. Failure is a necessary part of success, but the faster you can learn from your mistakes, correct them, and move on, the faster (and more profitably) you will reach your ultimate goal.

Want to learn more? Get all the details on this new technology in our white paper, Root Cause Deconvolution—The Next Step in Diagnosis Resolution Improvement, now available for download.

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22 July, 2014

uneven-heat-distributionIf you’re designing large die such as a system-on-chip (SoC) with high power demands, you’d better be thinking about how to get the heat out. Poor heat dissipation can lead to a sub-optimal packaging solution from cost, size, weight and performance perspectives.

Historically, designers assumed the die temperature was uniform. Not any more. Heating due to current leakage makes power dissipation less uniform, and thinner dies reduce the heat spreading capability of the die, creating greater on-die temperature variation.

Chip-package thermal co-design is particularly important when designing stacked three-dimensional integrated circuits (3DICs). The dies cannot be designed independently due to their electrical and thermal interaction.

If you need to understand the why, when, and how of thermal co-design, you need to read our new white paper, “7 Key Considerations for Effective Chip-Package Thermal Co-Design…A High-Level ‘How to’ Guide.” With detailed explanations of each step, it provides a clear roadmap through the process, and helps you avoid common mistakes and pitfalls along the way.

Don’t let global warming destroy your next SoC design!

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21 July, 2014

HELP-3No, that’s not really a cry for help, at least not from me. But I can imagine a lot of designers saying just that as they try to understand and implement multi-patterning requirements. LELE? LELELE? LELELELE? SADP? SADP SIT? Whhaaaatttt???!!!

And help we have. In spades. Our resident multi-patterning expert, David Abercrombie, not only writes extensively about multi-patterning issues, but he is a frequently sought-after guest for interviews, roundtables, and panels. But rather than making you search hither and yon for David’s insights and guidance, we’ve gathered it up for you in one convenient location.

Multi-Patterning Unmasked is your quick guide to a wide variety of multi-patterning topics. Need to start with the basics? We’ve got you covered! Struggling with debugging pesky MP errors that seem to multiply by the minute? David explains why that can happen, and how you can avoid it. Going cross-eyed trying to understand self-aligned double patterning? Multiple diagrams with detailed explanations clarify just how the process works.

Not only do you get quick access to all of David’s articles, but we also provide links to white papers, videos, and training classes. And we’ll keep updating the list as more information becomes available.

If you haven’t already, check it out! And keep it bookmarked for future updates…amaze and astonish your friends and colleagues with your insider knowledge and familiarity with the latest MP tips and tricks!

Of course, if you really want to help me, you can let me know what other IC design and manufacturing topics you’d like more information and guidance for. You can comment here, or send me a private email.

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10 June, 2014

The World Cup is here! Every four years, the culmination of hundreds of qualifying matches around the world brings the best national teams wc2014-balltogether for nearly a month of intense competition to determine the world champion football team (Sorry, USA, but it’s football everywhere else). New national uniforms are unveiled, shoe companies vie to sponsor the best players and teams with their most advanced technology, and the official ball is announced. Because every ball design provides slightly different performance qualities, the 2014 World Cup match ball, the Adidas Brazuca, was provided to all the qualifying teams back in 2013, enabling them to use the ball in training and friendly competitions to become familiar with its handling characteristics. This familiarization period before the World Cup matches begin ensures that all the teams can come into the competition prepared to play at their best, with no surprises.

What does this have to do with IC designs? Well, as the foundries develop a new process, they use a certain set of verification tools to establish the manufacturing requirements and design rules that help ensure adequate yield and performance at that process node. As a foundry converges on a final process, it releases frequent updates to the provisional design rules, based on the results of simulations, analyses, and test chips. A fabless company working at the leading edge must be prepared to quickly update and incorporate these changes into their design flows if they want to get to market first with the most advanced designs.

However, if that fabless company is not using the same verification toolset as the foundry, they have a problem. The foundry does not have time or resources during a process development to evaluate every verification toolset in the market against its design rules. Once a process is considered production-ready (although we know no process is ever really final), the foundry issues a final design rule manual. Other verification tool vendors can then validate their rule decks against this manual, but that takes time and effort. Design companies that were using the same verification toolsets as their foundries are already off and running to production, because they were in step with every change coming out of the process development phase. They didn’t have to wait for their EDA vendor to receive process certification from the foundry.

Like the World Cu2014-fifa-world-cup-trophyp teams, having the opportunity to use the same verification tools as your foundry means you can bring your best game to the field, with no surprises. By the time you are ready for tapeout, you already know how the process works, what its unique characteristics and requirements are, and how to best implement your design flow to ensure successful production and performance.

Gooooaaaaaaaaaaaaaaal!

Mentor Graphics Design and Verification Tools Certified for Full Production of TSMC 16nm FinFET

Mentor Graphics Supports a Common Signoff Environment for Samsung and GLOBALFOUNDRIES 14nm FinFET

Mentor Graphics Tools Fully Enabled for Intel Custom Foundry 14nm Processes

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13 May, 2014

Olympus-MP-buildWith the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased design sizes, and multiple design objectives can seem overwhelming, especially when your time-to-market targets get shorter every day.

What designers need is a flexible and powerful architecture that addresses multi-patterning and FinFET requirements while still helping design teams achieve optimal power, performance, and area across all design metrics. Our new white paper, FinFET and Multi-Patterning Aware Place & Route Implementation, provides a detailed discussion of the challenges presented in design implementation at advanced nodes, giving you a raft that will help you overcome the myriad challenges and bring your designs safely ashore.

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8 May, 2014

Debugging multi-patterning errors is hard without helpRemember learning your colors in kindergarten? Learning how to debug color assignment errors in multi-patterning can sometimes seem just as confusing. In Take Two of the Tech Talk videos on multi-patterning, David Abercrombie continues his discussion with Brian Bailey of Semiconductor Engineering about color assignment issues, and possible corrective actions.

More often than not, a color assignment error condition has multiple correct answers, or worse, multiple wrong answers. Designers can waste a lot of time “trying out” different coloring and formatting corrections. Understanding your options, and how to determine the optimal solution, can be challenging, but new tool functionality can provide more detailed debugging information to help designers make the best choice.

If you’d like to learn more about Calibre® Multi-Patterning functionality, and our patent-pending warning rings that help designers avoid creating new errors when correcting existing errors, check out the Calibre® Multi-Patterning datasheet, or read our white paper, Mastering the Magic of Multi-Patterning.

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7 May, 2014

Depending on how well your company implements it, IC Designverification can be a quagmire that slows down your design delivery and creates frustration and conflict between teams, or a springboard that lets you deliver high-quality designs ahead of your competition.

In a recent interview with Pradeep Chakraborty, our CEO, Wally Rhines, discusses the intricacies of design verification today, the biggest verification mistakes design teams make, and what companies should be doing to successfully integrate advanced functional verification technologies and methodologies into their work flows. By bringing verification teams into the design environment, companies can benefit from their expertise and experience, and avoid making architectural design decisions that create verification sinkholes.

Wally ends with his Top Five (sorry, David Letterman) recommendations for verification. List your own Top Five before you read the interview, then see if you and Wally agree!

If you’re interested in more information about the Mentor services mentioned by Dr. Rhines, click on the links below.

  • The Mentor Graphics Verification Academy helps organizations mature their functional verification processes with on-demand webinars, video training, interactive forums, and methodology “cookbooks.”
  • Mentor Graphics’ Consulting Services provides customized solutions to technical challenges on real projects with real schedules.

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