I have one opinion about electricity…if it’s invisible and it can kill you, it’s probably a good idea to avoid it. Now, some of my attitude is shaped by spending most of my childhood along the US Gulf Coast, where massive thunderstorms are an almost-daily occurrence during summer, and every little kid is taught to run for cover at the first rumble or flash. But that healthy fear means I still can’t (won’t) wire my own appliances, and I always struggle to remember the difference between voltage and amperage.
Fortunately for me, other people out there were not dissuaded from learning the minutiae of electrical circuits. Circuit verification and parasitic extraction at advanced nodes are facing a host of new challenges—finFET transistors, 3D chip assemblies, multi-patterning impacts, rising interconnect resistance, multiple power domains—and designers must ensure that their designs will not only function as intended, but will meet the exacting reliability and performance goals that today’s electronics require.
If you’re responsible for circuit verification or parasitic extraction, and you’d prefer to avoid major shocks during your design and verification flow, here are some good sources of information for you to peruse:
- Are Multi-Patterning Corners Really Needed for 16/14 nm?
Understanding the implications of multi-patterning and its effects on parasitic extraction will help designers determine the best extraction approach for their designs. Employing parasitic extraction tools that incorporate automated multi-patterning corner processing can help design teams reduce the runtime impact when multi-patterning corners are required.
(EE Times SoC DesignLine)
- Full 3D-IC parasitic extraction
Learn how you can use Calibre 3DSTACK to enhance an ‘ideal’ parasitic extraction strategy to create a full 3D assembly-level, device-level parasitic netlist suitable for simulation and circuit analysis.
(Tech Design Forum)
- Designing And Testing FinFET-based IC Designs
The introduction of FinFETs means that CMOS transistors must be modeled as three-dimensional (3D) devices during the IC design process, with all the complexity and uncertainty this entails. In addition, test and failure analysis is taking on new importance, because the critical dimensions of finFETs are smaller than the underlying node size
- SoC Reliability Verification Doesn’t Just Happen, You Know
Accurate and repeatable reliability verification is now a critical capability for both established and advanced nodes. Calibre PERC can help designers validate power intent at the transistor level, both in standalone IP and as part of a full SoC, in the same flow.
(Semiconductor Manufacturing & Design)
- Fast and Accurate Full-Chip Extraction and Optimization of TSV-to-Wire Coupling
This DAC paper discusses the modeling and extraction of parasitic capacitance between TSVs and their surrounding wires in 3D ICs. It proposes a pattern-matching-based algorithm that considers the physical dimensions of TSVs and neighboring wires, and captures their field interactions to provide a fast and accurate full-chip extraction.
(Design Automation Conference)
Now, it’s the red wire I need to watch out for, right? Or is it the black??…