Fabless/Foundry Ecosystem Solutions

You’re creating chips with high functionality, multiple operating modes, low power consumption, and extreme reliability—pushing the manufacturing process to the limit. But your advanced ICs are increasingly sensitive to the smallest manufacturing variations, and that affects both performance and yield. Mentor's Foundry Solutions can help you solve your design challenges.

21 March, 2015

Balancing on wobbly tightropes is something that chip designers get pretty good at. For instance, there is a fine balance between optimizing performance and minimizing leakage in a design layout. Dealing with the new requirements that multi-patterning (MP) introduces into a design flow creates many new tightropes to walk. Let’s take a deep breath and step right out to the middle of one of these ropes–I hope my observations here will provide at least a small net to catch you! Click here to read article.

21 March, 2015

Almost anyone who is active in IC design will be “in touch” with Electrostatic Discharge (ESD) at some time (pun intended). Preventing ESD-related IC failures remains something like black magic—at least it’s easy to get that feeling when you are trying to debug ESD failures. I/O and ESD layouts that resulted in excellent robustness in one IC product might suddenly create havoc in a slight product variation.

If you feel like you need to learn more about the mysteries of ESD, you might want to consider traveling to beautiful Lake Tahoe this May where the world’s leading ESD experts gather in a highly interactive conference called the International ESD Workshop (IEW). This year it’s at the majestic Granlibakken Conference Center and Lodge from May 3 – 7, 2015. This setting provides the perfect opportunity for participants to meet in a relaxed atmosphere and engage in discussions about the latest research and issues of interest within the ESD community. Learn more about it by clicking here.

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21 March, 2015

Embedded test compression was commercially introduced over a decade ago and has successfully reduced the size of IC test patterns and test time by well over 100X. However, growing gate counts at the latest technology nodes, as well as new fault models targeting defects within standard cells, are driving the need for even greater test pattern compression. A new approach employing internal test points is now available to further reduce pattern volume. Results gathered across numerous customer designs show that the EDT Test Points methodology can significantly reduce pattern counts while maintaining or improving test coverage. Learn more about the new technology in the “EDT Test Points” white paper.

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21 March, 2015

The road to low power IC design starts very early in engineering process, ideally at the specification and architectural design stages. It is here that major tradeoffs can be made and operational modes defined that will have huge impacts on the overall power consumption of a device. However, to make sure those design intents are carried through to the working silicon, and that you don’t leave power savings “on the table” due to a poor implementation, you still need to pay close attention to detail at the physical design stage. Especially if you are moving to advanced nodes with finFET transistors, your IC design tool needs to be finFET-aware to ensure you realize the lowest power possible from the actual physical layout. Place and route capabilities such as power-aware RTL synthesis, activity-driven placement and optimization, CTS (clock tree synthesis) power reduction, and concurrent optimization for dynamic power and leakage can help make sure you get the most from the move to finFETs. Learn more about physical design optimizations for power in this article “FinFET Impact on Dynamic Power” by Mentor’s Arvind Narayanan.

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3 February, 2015

The 40th SPIE Advanced Lithography conference will be held at the San Jose Convention Center, February 22-26. dsaibmOver the past few years, this conference has grown in scope to include emerging patterning technologies like directed self-assembly (DSA) and design-process-technology co-optimization. Underlying all the presentations, posters, panels, and hallway chatter are the common goals and challenges: keep the fabs working and yields high, while controlling cost and turnaround time, all as the laws of physics work against you.

One key component of managing modern manufacturing is computational lithography, which includes:

  • Optical proximity correction (OPC) and resolution enhancement technology (RET) software and methodologies that achieve the maximum possible lithography entitlement
  • Software, applications, and methodologies that allow foundries to increase their productivity, which reduces development cycle times and associated costs
  • Management of the post-tapeout flow

You’ll see plenty of this type of technology at the conference. There are papers on incorporating DSA in multi-patterning, analyzing lithography hotspots with pattern matching software, enhancing local printability in sub-14nm nodes, model-based mask preparation, new modeling of 3D effects, and managing OPC jobs for better productivity and use of resources. These technologies all help maintain reasonable turnaround times for the entire post-tapeout flow and manage foundry production costs.

The importance of modeling

We talked to John Sturtevant, our director of modeling and verification solutions at Mentor Graphics, about some of the hot topics in computational lithography. He said that there are significant modeling challenges associated with the 14 and 10 nm manufacturing process nodes, particularly the need for accurate and fast simulation of three-dimensional phenomena associated with the mask, wafer, and resist.

“3D EMF effects associated with mask topography have been effectively modeled for many years,” Sturtevant said, “and to support 14 nm, we added refinement of edge-to-edge crosstalk signals in DDM.” This enhancement leads to significantly better matching to rigorous simulation, with very little runtime impact. Using the crosstalk DDM library results in better wafer fitness, especially when the mask absorber sidewall is optimized in conjunction with mask bias, he said.

Sturtevant pointed out that formerly “non-critical” implant layers now pose a significant OPC challenge. Underlayer topography models, which capture the complex array of wafer topography effects, have been deployed for 14 nm. These models are being expanded to better represent the impact of active finFETs, and the results for pre- and post-poly layer implant models have been excellent.

There is also new focus on the photoresist model. The 14 and 10 nm nodes feature extensive use of negative-tone develop (NTD) resist processes for the patterning of metal and via layers, due to the intrinsic aerial image advantage of a bright field mask. These NTD resist processes have unique shrinkage and develop rate properties compared to the traditional positive-tone processes. Sturtevant says Mentor has modified the CM1 model to support new NTD-specific modelforms, with a 40-55% improved accuracy in predicting wafer results. They have also rolled out improvements in the prediction of resist toploss and scumming, as well as SRAF printing for both PTD and NTD cases.

DSA is now on the near horizon, and compact models predicting the assembly of vias inside of guiding patterns are already available to assist in development efforts. An important consideration for these models is to ensure the proper 3D formation of the vias. You can expect to hear a lot about DSA, and computational platforms for DSA, at SPIE Advanced Lithography this year.

So, if you’re involved in design for manufacturing or post-tapeout engineering, you should be SPIE-ing on these new technologies and techniques. Hear the presentations, talk to the authors, and learn how you can meet your goals and master your challenges.

February 22-26, 2015 at the San Jose Convention Center!

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28 January, 2015

Every time I see “3D IC’ somewhere, I’m reminded of that silly kid’s chant we used to yell at each other in the playground, “R U A B? I C A B! O, O, O!! A B I C!!” Apparently that was much more amusing at the age of eight, but it has stuck in my head all these years. Go figure…

Which has nothing, really, to do with what I want to talk about, which is 3D IC design and ESD protection. Designers have long known how to protect their single die designs against electrostatic discharge, to the point where ESD protection is pretty much built into the design and test flow. When it comes to 3D designs, however, things are suddenly less clear, and less well-defined. How do you know a 3rd-party die is properly protected? What about protection between the die? What about TSVs?

Enter the Global Semiconductor Alliance and the ESD Association. Together they have authored a detailed papGSA_3DIC_ESDer that addresses the issues of ESD in 2.5/3D packages, and presents countermeasures that design teams may wish to consider in the design, development, fabrication, and assembly/test of such devices. It contains lots of acronyms, including my new favorite (KOZ!), as well as practical, easy-to-read explanations and advice. And pictures! Did I mention the pictures?

How do I know this paper is worth reading? Well, two of the contributors just happen to be colleagues of mine—Matthew Hogan and Roman Gafiteanu. These two are sticklers for detail, and passionate about sharing their knowledge with others. The small amount of time they’ve spent explaining these topics to me is nothing compared to the effort they, and the other contributors, put in to ensure this paper contained all the information and detail designers would need to understand and apply the strategies and techniques they describe.

Have I intrigued you? Want to see a copy of this most excellent paper for yourself? Should I keep you waiting any longer?

Okay, here you go: Electrostatic Discharge (ESD) in 3D-IC Packages

I C U smiling!

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18 December, 2014

2015-CubsThat time of year is coming…the old calendar comes down, the new one goes up, and we look at all those days ahead of us and think…THIS year, the Chicago Cubs will win the World Series! Okay, we don’t really think that, but it’s one of those forlorn wishes that keeps hanging around.

What you really think is that THIS year is different, new, full of possibilities. You’ll lose weight, organize the garage, get ahead of all those projects on your desk, solve that niggling design rule error that eluded you last week, or get that tapeout to the foundry a week ahead of schedule. Whatever it is, you’re resolved to do it/start it/finish it/solve it in the new year.

And here at Mentor, we want to help. Can’t do much about your weight or garage, but I’m happy and excited to announce the addition of Solutions resources on our Fabless/Foundry Ecosystems Solutions website. Each of our Solutions will be chock-full of resources to help you clearly understand the issues in a particular design and verification topic, and provide you with the information and guidance you need to improve your design and manufacturing processes.

SolutionsWe started with multi-patterning, because, well, we listen. Multi-patterning is one of those new requirements that a lot of design teams are wrestling with. Implementing multi-patterning is not nearly as simple as it might seem, and we’ve done our best to document the complexities and hidden traps that can thwart your best efforts.

Other solutions, including advanced fill strategies, 3D-IC design verification, and reliability verification are on their way. And if there’s a topic area you’d like us to consider, drop me a note. The whole point of this website is to provide you with the knowledge and support that can help you and your company achieve your goals. That’s MY resolution for the coming year.

Happy New Year!

15 December, 2014

bootcampA few weeks ago, I introduced you to the start of a DFT Bootcamp series for those of us who wouldn’t know a DUT if we ran into one.

Maybe you design ICs, but someone else adds the test circuitry to your layouts. All you know (grumble, grumble) is that those additions can change your design’s performance, increase the die size, and require additional verification. But even if you’re a systems or board designer, there is value in understanding the basics of design for test (DFT) techniques and technologies. Learning more about how those digital ICs are built and tested may help you understand the challenges of IC design, why certain test circuitry is needed, what it does, and how DFT can help ensure those components will operate reliably and properly in your product.

Accessible anytime (4 am!) and anywhere you have connectivity (Starbucks!), this bootcamp series takes you through the basic elements and processes of DFT. After completing all four articles, you will astound your colleagues with your new-found understanding of DUT and BIST and ATPG. And you won’t even have to shave your head or do push-ups.

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11 December, 2014

Giardia-cdcParasitic extraction is a pretty commonplace procedure these days in IC design. As geometries got smaller and more tightly packed, the resistance, capacitance and inductance of interconnects became significant enough to affect circuit performance. Accounting for these parasitic effects became a tapeout requirement, since they could cause signal noise and delays, as well as IR drop. EDA vendors stepped up to the plate with parasitic extraction tools that could calculate the effect of parasitics and integrate this information into the circuitry analysis.

But a funny thing happened on the way to the leading-edge nodes. We introduced new geometries like FinFET transistors, created new chip structures using silicon interposers and 3D stacks, and integrated devices like MEMS and silicon photonics into our IC designs. All of those changes require new approaches to parasitic extraction, which has led to new tools and techniques designed specifically to address the challenges presented by these new designs.

For those of you already struggling to produce accurate extraction results for these new design elements, the help you need is here. If you haven’t yet begun working with these components, here’s your chance to get ahead of the game. The resources listed below outline many of the issues that must be considered, and introduce new techniques and tools developed to assist designers in performing accurate, timely parasitic extraction for a variety of configurations and design features.

Those parasites will never know what hit ‘em…

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15 November, 2014

test-picAre you a calm person? Or are you easily irritated? We all have our limits and pressure points—just like a design layout. Certain geometries may have a high failure rate in production. Circuitry may fail when confronted with an ESD event. When your design passes verification, does that mean it’s all good? In theory, yes. In reality, everyone knows that the real world is a tough place for electronics. Environmental stresses may reveal previously unknown fault points in a design. Some defects may not show up until the chip has been in operation for a long period of time.

That’s where test comes in. By adding test structures to a layout and running designs through strenuous and exhaustive tests, a test engineer can pinpoint those areas of a design likely to fail in real world operation. Reporting this information back to the design side lets test and design engineers  work together to eliminate potential design failure points and implement design layouts that will operate as intended for the planned life of the chip.

But if you don’t know much about IC test, you’re not alone. Which is why Bruce Swanson, Ron Press, and Martin Keim created the Design for Test Bootcamp series in the EDN Test & Measurement Design Center. In this series of blogs, they’ll introduce the basics of DFT and explain some of those unfamiliar terms and processes, like scan test, fault models, test compression, and much, much more. The first two blogs are already up, so take advantage of their expertise and learn how to avoid a market disaster for your products.

As for your own meltdowns? Maybe this will help…

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@Mentor_Foundry tweets

  • Matt Hogan discusses the technological and societal requirements needed for the adoption of self-driving cars http://t.co/cPZehXIj6B
  • Arvind Narayanan offers guidance on how to manage dynamic power of finFET designs during physical design http://t.co/zXxEH4nDpi
  • This paper discusses a novel approach to a physical verification flow for hierarchical analog IC design constraints. http://t.co/qwQp2lhvMd

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