Foundry Solutions

You’re creating chips with high functionality, multiple operating modes, low power consumption, and extreme reliability—pushing the manufacturing process to the limit. But your advanced ICs are increasingly sensitive to the smallest manufacturing variations, and that affects both performance and yield. Mentor's Foundry Solutions can help you solve your design challenges.

21 March, 2014

siliconphotonicsPhotonics technology isn’t new, by any means, but what is new is the drive to leverage high-volume silicon-based semiconductor manufacturing foundries and processes to build chips that can create, sense, modulate, and transmit light. So says Michael White in his latest SiliconEdge column on Electronic Design.

The biggest challenge in applying CMOS foundry processes to silicon photonics is creating device models and adapting EDA design tools and processes to characterize, measure, and simulate the precise curvatures required by silicon photonics interconnects. Progress is being made—test chips have been generated with the new tool flows, and foundries are preparing to move to volume production. The next step is for IC designers to begin developing applications that incorporate the capabilities of silicon photonics.

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20 March, 2014

I practice yoga because it helps with my flexibility. Of course, that’s a little like saying that lighting a candle helps with heating your house, but I digress. The point is, flexibility is generally a good thing, and that holds true for 3D ICs and their test strategies. As discussed in the Electrical Engineering Journal, a flexible 3D test strategy that uses a “plug-and-play” architecture allows multiple tests to use the same interface, simplifying the introduction and use of multiple tests. Structuring the architecture around the IJTAG standard also makes it easier to adjust to and adopt future test features. Having a test strategy you don’t have to bend over backwards to implement every time something changes? That’s true flexibility.

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19 March, 2014

Trailblazers, followers, and stragglers…semiconductor companies have usually always sorted themselves out along these lines. At 20nm, though ,we’re beginning to see a shift in these classifications that is affecting both technology node adoption and market strategy. Only a few companies are moving to nodes at 20nm and below, while many of the typical followers have decided to stay at 28nm for the foreseeable future. Meanwhile, those in the rear of the march to tomorrow have, in many cases, decided to create market differentiation at the older node by adding complexity and functionality to existing designs. How are these changes affecting the IC design market market? Christen Decoin explains in his latest article on EDN.

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17 March, 2014

automotiveDFTIs design-for-test the forgotten stepchild of IC design? Not any more, and DFT engineers can, in large part, thank the automotive industry. The number of processors built into a vehicle is steadily increasing, as we all know (okay, maybe not that guy driving the 1969 Chevy Camaro). These chips have to meet very high standards for quality and reliability, which means the companies who make them need both high-quality manufacturing tests and in-system tests. And of course, they’re supposed to do that without increasing test time or cost. In this article from EDN, Ron Press discusses how designers are making use of new test technologies and tools to meet the new standards.

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14 March, 2014

Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor Manufacturing & Design, Jeff Wilson explains how an effective ECO fill strategy can help reduce runtime, manage file size, and minimize timing impacts.

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3 March, 2014

The semiconductor industry can (and does) argue about when extreme ultraviolet lithography will be ready for production. However, the actual dates are irrelevant to those engineers who must prepare OPC tools and processes for the EUV-specific effects that will have to be managed in manufacturing. They are busy now, evaluating the impact of such challenges as the distortion caused by EUV shadowing. In the January edition of Solid State Technology, Fan Jiang takes an in-depth look at this EUV effect, and the model-based solution that has been developed to resolve the resultant imaging errors.

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3 March, 2014

David Abercrombie recently met with Brian Bailey of Semiconductor Engineering to explain many of the concepts and issues of multi-patterning that he has been writing about for the last couple of years. If you want to understand the basics of multi-patterning requirements, 12 minutes is all you need to check out their first video: Tech Talk: Multipatterning on semiengineering.com.

If the video piques your interest in learning more about multi-patterning, you can also download a copy of David’s white paper, Mastering the Magic of Multi-Patterning, from Mentor.

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19 February, 2014

The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, typically referred as a value change dump (VCD), logic simulation is used to generate the complete activity suite. In vectorless mode, the PG analysis tool generates this activity suite. The PG dynamic simulator can’t differentiate between an activity suite generated from either mode, but the quality of the dynamic PG analysis is driven by the quality of the activity suite. So, which one should a designer use? Marko Chew explains the details of both approaches in Stimuli-Driven Power Grid Analysis on SemiconductorEngineering.

Still craving more of the gritty details? Dr. Farid Najm of the University of Toronto worked with Mentor Graphics to create a white paper—Vectorless Verification of IC Power Delivery Networks— explaining just exactly how a practical application of vectorless verification can provide early, accurate, and fast power grid analysis, even with limited circuit data. Download your copy today!

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18 February, 2014

In Standards & Travels on EE Times, Bruce Swanson reminisces about a trip he took to Europe, long before there were cell phones, a common currency, or even the Internet. Dealing with different languages, different currencies, and different local customs took time, was a bit frustrating, and sometimes led to mistakes (WHERE is this train going?!). His experiences on that trip came to mind recently when he was thinking about the challenges and complexities of accessing, integrating and testing the different parts and pieces of an IC. A proposed IEEE standard (P1687), commonly called the IJTAG standard, provides a general-access test mechanism to the embedded IP within all levels of the design hierarchy. Bruce explains why that’s so important, and even provides a number of links for those who want the gritty details.

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14 February, 2014

At advanced nodes, variability issues lurk behind every design mode, power state, process condition, and manufacturing step. Yet designers must find a way to balance the optimization of multiple operational modes and design corners against the aggressive performance and power targets demanded by today’s fast-moving markets. Concurrent analysis and optimization during place and route operations can provide the necessary quality of results. To learn more, check out Sudhakar Jilla’s article on Tech Design Forum.

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