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Altera goes back to 1984, when you could get 720KB on a floppy. After all these years, FPGAs still provide the right mix of being flexible like software while still being fixed and fast like hardware. Why does this cool idea persist in new product designs?
Fortunately the big FPGA vendors, such as Xilinx, have continued to invest in R&D. Innovations from internal genius and acquisitions have resulted in some irresistible features. With Gigabit transceivers, gaming level calculations, and advanced packaging, FPGAs have been advancing like pioneers. FPGAs also benefited from others’ investments. Millions of consumers like me who buy a new computer every year have funded the IC manufacturers while they perfect techniques FPGAs adopt. I have yet to attend a design meeting where the marketing people can dream on the white board more than the FPGA could handle.
Willing and Brilliant Nerds
Designing an FPGA requires the insight to imagine the whole system with fluid boundaries of hardware to software. Designers must have hardware dude discipline, but also software hacker creative problem solving. You have to start with the understanding of clock domains and hard logic, and keep some details like timing. But after that, you have to let go. Trust the compiler to handle the nitty-gritty gate details. This frees up your design energies to redefine the problems by pushing functionality around between blocks, and even sometimes on or off chip. This blend of hardware and software has matured to the point where the right degree at an engineering university is no longer CS or EE but a hybrid. Not all engineers do well thinking in the in-between world of hardware and software, but they are out there.
Since there is a whole layer of detail in FPGA design that is not nailed down as in an ASIC, FPGA design necessarily leans on automation. FPGA synthesis, routing, and Mentor design software combine to manage a huge pile of interacting details and provide users with top level controls and constraints. Your high and mid-level understanding directs built-in rule engines to execute the minutia. Having the capability to reorganize your pin-out, for example, is useless if you don’t have the confidence you are doing it in compliance with all those tables and notes in the 2000 page data sheet. Even better is the automation to kick off an optimization engine to unravel your I/O connections to the board instead of manual pin swap trial and error.
FPGAs Boldly Go
Since there is still money to be made from quickly accomplishing the previously impossible, FPGAs continue to expand into new areas. For over a decade I’ve seen “Experienced FPGA Designer” repeatedly pop up on local most wanted listings and according to this weeks’ job boards that isn’t slowing down. The chips, the software and the talent are all out there. So, be fearless, dream up the impossible, and let FPGAs live up to their reputation.
While recording a how-to video about placing parts on a schematic, one part is showing off the hyperlink to the datasheet. That is moderately cool in the hardware designer circles, but what happened when I clicked the link was beyond cool. To see the whole picture, I have a Windows-Dell and a MacBook Pro next to each other on my desk. I use virtual machines (VM) to keep all the various flavors of Mentor software at my fingertips. So, I had completely forgotten that I was on a Windows VM running on a Mac. Imagine my surprise when a Safari window opens on my Windows7 screen showing me the data sheet.
The windows ODBC configuration got involved, but I have Access installed on the Mac side of things, not windows. I can say for sure I started in Windows and ended up in Mac OS X world, but which application call ended up jumping between the two worlds wasn’t immediately obvious. It just works. I’ve been noticing how shared volumes and cross platform system calls allow the Ying and Yang of operating systems start to play nicely together. Now it is time to sit back and enjoy. For those of us survivors of Windows 3.1 and IBM Warp2, it is a wonderful life.
The most common question I get while evangelizing for VM’s is, “Ya but what about performance?” I estimate the software I normally have to wait on runs about 3 times faster on my computer with a solid-state hard drive. Then I take a maximum of 5 percent performance hit with the VM overhead. So be fearless; weave your operating systems together. And, buy the fastest hard drive your budget allows.
After years of pooh-poohing AMD, Intel had to admit you could get more data throughput switching to a high-speed serial approach. Let’s say high-speed serial is in the 1 to 10 Gbps range per lane, and use PCIe as an example. This is where the benefits become irresistible and the behavior becomes unexpected according to the previous rules of layout design.
The PCIe specification helps define the different pieces of a general high-speed solution when it breaks down the interface into the transmitter, receiver, and channel. Much of the benefit from high-speed-serial comes from the transmitter pre-emphasis, receiver equalization and packet management. But once you are in layout, the design challenges are all in the channel. The copper routes and surrounding physical structures all effect how the high-speed signals propagate. This sounds like an RF design for good reason — as the speeds increase, trace geometry and surrounding materials contribute to channel characteristics as if they were discrete components, and discretes don’t display the reactive behavior you expected. This is where the schematic tells the intended behavior. Only after the layout is done is the design showing real electrical behavior.
Once you have your RF hat on and are looking at the layout as part of the whole design, the required design disciplines make sense. The first part of the design solution is setting up a routing physical environment. This is a 3-D design of all the right materials and plane arrangement around a high-speed routing channel. The performance and modeling of a high-speed differential pair starts with a very narrowly defined routing environment — surrounding material, planes, and geometries. Generally speaking, we build the board structure around the channel and that justifies making the assumptions behind a classic strip-line topology. This means we already have a plan for the board’s connectors, layer use, and general physical arrangement. Ensuring this routing channel setup is established first, and stays in place must be established before routing.
The other common killer assumption is that power and ground are golden. As design speeds’ edge rates exceed the traditional discrete component frequency behavior, the stable power assumption falls apart and the power distribution network (PDN) becomes part of the SI design. Your transmitter buffer output model assumes good power across the whole frequency spectrum. So, before it is even worth the time to start routing a high-speed differential pair, a solid PDN must be in place for the transmitters. There are two good ways to ensure this prerequisite is met: massive overdesign or power integrity (PI) simulation. I must admit I’ve done both, but recommend simulation.
Now that your routing environment is established, the point-to-point topology of a high speed pair would at first seem like the route would be boring, but the fun part of high-speed layout starts here by making this route a high quality transmission line. The two main things to keep in mind now are keeping the phases matched and keeping the characteristic impedance matched.
The difference in phase of each leg of a differential pair comes from pin fanouts, different propagation speeds on different layers, and different structures, such as vias. The routing tool can keep the lengths matched along the way, but it is up to you to ensure the transition from the channel to the chips also keeps the electrical lengths matched and to avoid unbalanced copper structures. With all those considerations taken care of, laying down the route is all about the characteristic impedance. Antipads, stripping out non-functional pads, teardrops, and rounding are all high-speed features striving toward the same goal — matched and unchanging characteristic impedance. Since all of the copper in all three dimensions contribute to the characteristic impedance, every copper detail is part of the electrical design.
These details needed for success are electrical constraints of physical design. The path to success is to enter these constraints as layout rules and allow dynamic recalculation as the physical design work progresses. The visibility that you are still on the path to success is simulation. Until you have years of RF design experience some of the things that change your characteristic impedance are not obvious, so a post route SI simulation is at least as important as a SPICE simulation of an analog filter.
Do you have a favorite reference design you use as a starting point? Please leave it below.
Since FPGAs, field programmable gate arrays, are in their very nature fluid and changing, how do you force them into your electronics design techniques that all assume fixed parts? Hardware design uses, well… hardware, physical chips and resistors that have fixed functionality. We pull parts from libraries, wire them up, lay etch and build the gizmo. FPGAs throw out the definition of hardware and mess up that design flow from libraries to schematic to PCB layout, but their flexibility is worth the trouble. There are two main sticking points, parts for a schematic and connections for the layout.
FPGAs’ hundreds of user pins show up on several to dozens of schematic symbols to place an FPGA on a schematic. Normally a librarian would build up a set of symbols with helpful pin names, like “Data.” But as the FPGA functionality changes with each compile, that plan won’t work. So the options are to keep the pins not-locked-down, or make all the symbols very generic, “Bank 2 IO_23.” I was just in Texas negotiating a truce between two different design centers who took different sides of this debate. As long as your tools are powerful enough to accommodate all the nuances, both the librarians and the FPGA schematic designers can peacefully coexist. Which is another reason to buy I/O Designer to tie the disparate tools together with automation.
Assuming you plowed through to the layout, now the layout designer has two problems. His connections are all scrambled into a knot like no one planned out the chip, and they keep changing. The root of these problems is the same, the decision on what signal goes on which pin is done entirely by the FPGA compiler with little regard to the physical design. An experienced designer can improve on that and there are some Xilinx tool features to facilitate the FPGA designer who cares. But there is also a uniquely qualified design option in Expedition I mentioned earlier, I/O Designer. This little FPGA gem can remember the FPGA pin capability rules while looking at the physical layout orientations and connections. It unravels the connections turning a layout nightmare into an orderly set of parallel lines.
I’ve found using all the Expedition tools I can relieves most of the headaches caused by FPGAs. How do you deal with trying to design with a part that keeps changing?
If you play well with others, concurrent PCB design these days just makes sense. As ATM’s have proven, you can expect a high reliability, multi-user database to work fast… enough. The benefits of having multiple layout designers all working at the same time start with a faster design cycle, but there are more benefits if you share using a tool with built-in parallelism. You would not expect your cash withdraw for the price of a movie to lock out and stall everyone else from their request for a few dollars, not even for a few seconds. Concurrent design software is also instantaneous.
With Mentor Graphics Expedition tools, like DxDesigner and CES, parallel access is part of the framework. I always smile when people ask, “Where is the save button in DxDesigner?” There is an adjustment here realizing you aren’t working alone and off-line. Your work is real-time and shared. It’s your choice to just enjoy the environment or get your geek on and look a the underside of the tools. For concurrent layout, Mentor has a few papers on how and why you should at Mentor.com. Here I want to show you the coolest part, force fields.
In the photo above, if you turn on concurrent layout design and let Mentor software worry about the details, the only thing left to wonder about is what part of the design do I own right now? That is what force fields are, your bubble, an impenetrable sphere of influence. Wherever you are no one else can lay etch right across your toes. And, as you are working on layout or going for coffee, your bubble grows and shrinks as appropriate. There is no need for partitioning or complex branch and merge sharing coordination. So dive into the parallel world and get ‘er done.
In case you didn’t get the opportunity to go to PCB West 2012 in September, my favorite moment was the fabrication capability update from StreamLine circuits. Overall, the crowd was already noticeably more upbeat and energetic than the last couple years. But in a room of over a hundred nerds wearing jeans and button-down shirts, there were outbreaks of murmuring excitement when the latest board cross-sections were shown overhead.
We paused on the picture of a board with 1 mil trace thickness and 1 mil separation while plenty of questions came up about the whole fabrication process. What caught my attention was that the new limiting factor is hole to different-net-copper, not traces or drill annular rings. Starting with the assumption that you are using the latest equipment, and you run all types of boards through it to keep it busy, laser drilling and automated optical alignment become features you get without paying extra. High-density-interconnect designed boards may now quote for less. Using a couple of outer layers as build-up layers with blind and buried vias means a couple less plane layers in the whole stack-up, which saves money. Yeah! I get to finally use HDI without looking extravagant. The thinnest 4 layer board cross-section shown was 5.4 mils thick. It is OK if you are as unabashedly tech-nerd as I and you just said “Wow.”
It was a great time and I recommend PCB West especially for the design sessions. Hope to see you there next year!
Tags: PCB Innovation
In a December article I wrote that was published in CircuiTree called “A Fresh Look at MicroVias”, I presented the value of stacking microvias in the context of increased route density. The full article can be found here: http://www.circuitree.com/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000953428
In this blog, I am interested in getting feedback about stacking or staggering microvias so that we can get a sense of how quickly (or not) the industry is moving to stacked microvias. From what I can determine (based on numerous visits to design centers and fabricators) staggering microvias is still more common; however, more and more fabricators are offering stacking methods not only on 2+N+2 HDI configurations; but some fabricators are creating boards with multiple buildup layers with just a two layer inner core. Even more advanced are the boards that are 100% buildup layers.
Has your company evaluated stack methods? Is the additional cost or the current limit on number of layers the primary reason for not moving to them? Maybe the fabricator you are working with can only stagger microvias?
Please let us know what your experience is and what you expect your company to do in the future. It would also be interesting to note which segment your HDI designs target; for example, handset, computer, networking, etc.
I am wondering how common it is for PCB designers to have two monitors. Sometimes when I look at demos of our products, it appears to me that with interaction between dialogs and graphics, it would be a lot easier to just have two monitors, one for the graphics, one for the dialogs. What kind of setup do you have? What % of the PCB Designer community do you think have dual monitors?
What features would you like to see improved or added to interactive routing? I am asking this question for two reasons. First, I suspect that what you want may already be available but it is not obvious. Second, in a never ending quest to improve interactive routing, I would like to know what is of interest to users. Yes I know there are hundreds of requests for this and that in our Support Net and enhancement databases and believe me, I know of many things that can be improved. But this is a blog and a good place to discuss this stuff!
While we are on the subject of user interfaces, what about Personalized Menus? They are an optional method in Office 2003, accessed through the Customize dialog. They don’t exist in Office 2007; but since there has been general agreement (at least from most of the people I discuss it with) that the Office 2003 Menus, I thought I would bring them up to see if they are preferred or not.
If you uncheck “Always show full menus” then you will get the Personalized Menus that look like this:
The double arrow at the bottom is a cascade menu (double arrow) that shows you the menu items that you have used infrequently. The intent is to only display those menu items that you use regularly. Apparently the algorithm to determine which items should be hidden in the cascade; but it reportedly does a good job.
What do you think?
Do you use Personalized Menus?
Considering that some Menus may be quite long in Expedition PCB, is this a reasonable method to shorten the menus?
Or, do you use toolbars mostly and don’t visit the Menus very often?
Would you be interested in a Favorites Menu in which you could put your favorite menu items?
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- FPGAs are Still Cool
- Don’t Fear the VM
- High Speed Serial — Differential Pairs Done Right
- How Do You Design with FPGAs?
- Sharing Your PCB Layout
- Fabrication Capability Update from PCB West 2012
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