Don Kurelich's Blog

46th DAC – Value Update

Who got value out of DAC?  Many have already commented on the negative aspects of DAC this year; lower attendance, smaller booths, split-layout, less market-splash.  My opinion is quite different.  I enjoyed it and appreciated seeing innovation at-work. 

Attendance may be down, but focus is up.  The people that travelled to DAC had a purpose.  No company was sending Engineers to pick up vast quantities of trinkets for the office.   I found the focused customer meetings to be better than in prior years. They were coming to find solutions to their problems. 

Customers do have problems, problems that have only gotten worse in today’s economy.  They have issues keeping power-consumption down as devices grow in size and move to more advanced process nodes.  They have issues dealing with design complexity coming from more integration of IP blocks, high-speed I/O, processor subsystems, and large mixed-signal content.  Luckily, EDA is responding.  There were quite a few companies targetting these needs with innovative products – innovation looking for users.  Isn’t that what DAC is all about?

I wanted to highlight the main groups of technology I saw and help provide the managers, those  making the business decisions to invest, an idea of what they should expect from these new tools and why they are a good use of their R&D dollars.  Remember, as a manager, you can throw more bodies at the problem, buy faster machines, or invest in higher-quality tools. 

ESL: Implementing an ESL flow provides benefits in multiple ways.  First you get a functional model of your design that allows the team to validate the system (customer) requirements early.  New modelling techniques allow more accurate power and timing information to be included in these models, providing the ability to try multiple architectures to maximize performance, minimize power, lower cost and cleanly partition the design.   ESL Synthesis tools can take pieces of your system model and create RTL, with much lower effort than hand-coding.   Companies who implement an ESL strategy will see higher-quality designs and lower R&D and silicon costs. 

Advanced Functional Verification: There are more re-spins of silicon due to functional errors than anything else.  Throwing more verificaiton engineers at the problem is not economical.  Face it, you need to build an advanced verification platform with an efficient methodology that facilitates multiple levels of abstraction (enable TLM, for example), allows easy interconnect of verification IP, provides information on coverage (know what has been tested and what’s left), and will provide facilities for directed and constrained-random tests.  Mentor supports an open standard called OVM; it’s robust, proven, efficient, and FREE.  There was quite a showing of Formal tools which allow more exhaustive verification of pieces of your design.  My favorite has been clock-domain-crossing (CDC) tools as they efficiently traverse your design looking for ALL clocks and validating that all signals that cross clock-domains are properly synchronized.  You simply cannot lint or inspect your desings to find these errors.  CDC tools are fast and effective, not to mention they require no testbench or vectors.  Power-aware simulation, verification for your low-power structures, is also a growing neccesity.  These tools verify the logic that controls different low-power modes (standby, low-power, high-power for example) and that the appropriate isolation and retention logic has been applied.  Higher productivity awaits our decsion. 

DFM: A much talked about topic, but not widely adopted.  In essence DFM tools bring semiconductor manufacturing information to the designer.  More information allows the design teams to desensitize their designs by removing variability (performance, power, timing…) .  You can analyze your design and account for yield-limiting structures.  Engineers are often hesitant to deploy DFM tools as they want to know EXACTLY how much yield will be impacted – that’s very tough to quantify.  Using these new tools, you will see higher-quality designs (wider design margins), better yields and higher reliability.  Sounds like a no-brainer.  Physical Verification is also coming to the rescue with Electrical Rules Checking (ERC) that can help find issues with things like complicated ESD structures.  Equation-based DRC allows more sophisticated and compact rules to be written that more accurately describe the process limitations so you get higher performance and density.  Cool stuff.

Physical Implementation: Often called just place-and-route (P&R), this field has greatly expanded in sophistication and complexity.  Being driven by more advanced process nodes and low-power requirements, P&R tools need to optimize performance and close timing across multiple process corners and operating modes (MCMM).  I’ve seen requests for up to 100 mode/corner combinations on a single design.  Due to tool limitations, large designs have traditionally been broken into blocks (black, white, glass and other cute names) and had their timing “modeled” at the top-level.  This pushes many timing violations into the ECO flow, delaying tape-outs and creating non-optimal designs.  Luckily, a new generation PD tools can read-in entire chips (and I’m talking >100M instances) flat, where full visibility allows more optimization and quicker timing closure.  There is also a trend to integrate DRC tools into the P&R flow that provide DRC-clean designs first-pass out of the router, further reducing ECO cycles.  I also saw neat technology for optimizing clock-trees that significantly reduces power, while providing better less skew (more timing margin for PD). 

Economic times are tough and every company needs to be more productive.  EDA is all about productivity, and it shows.  Innovative EDA technology is out there, let’s get it deployed.

Tags: CDC, CTS, DFM, DRC, ERC, ESD, esl, Formal, low-power, MCMM, P&R