David Wiens' Blog

TLA 2011 Is Just Around The Corner!

The 2011 Technology Leadership Awards competition starts next week. This competition showcases the best PCB designs (and designers) from around the world representing all major electronics industries.The critical dates are:

• August 2: Site is open for new entries
• September 30: Deadline for entries
• November 17: Winners announced

Check out the 2010 winners and review the details of last year’s overall winner below to get an idea of the designs that get submitted.

2010 Technology Leadership Awards: Overall winner

The 2010 TLA competition featured stiff competition in all categories. In addition to winners in each industry category, an overall winner was also selected. GE Intelligent Platforms won this award with a ‘military & aerospace’ category entry.

Design team: Paul Curran, Mike Tapp, Rob Savage, John Digby

End product use: Rugged 6U VPX single board computer. This specialist family of products is aimed at high performance mil/aero applications.

Stats:

Design challenges:

• Design for…signal/power integrity, cost and manufacturability.
• Complexity: 3,500+ nets; 20,000+ connections; 11,600+ vias; 8,500+ components; total 20 BGAs placed on both sides – several quad flat packs with 0.4mm pitch also used.
• Thermal management: Processor was low power (30W), but still needed to place close to a cold wall due to operation at temperatures up to 85C. All components had to be rated for -45C to 85C for ruggedization.
• Mechanical: Mezzanine plug-in cards dictated low profile placement regions.
• Buried vias: Reduced buried via pairs to cut costs – increased routing challenge.
• High-speed signaling: Serial Rapid I/O, PCI-X, DDR3 – significant constraints with tight tolerances. Placed solid continuous ground layers on either side of over 500 diff pairs to minimize impedance discontinuities.
• Power: Managed trade-offs between power consumption and thermal management. Ensured that the PCB could deliver the required 30A current.
• Significant effort taken in placement to ensure thermal efficiency, effective power delivery, and sufficient routing channels including tuning space.
• 14 power rails – placed on two internal layers – shielded signals from power noise with ground plane on either side. Manually increased power trace widths wherever possible to increase current capacity for critical devices.
• The stack-up created for this design has been successfully used for other designs and has become the new standard.

Design tools:

• Expedition Enterprise flow
  • I/O Designer: “The major design challenge was routing the processor and connecting components. Because the number of routing channels and layers was limited it was important to reduce the number of crossover connections between the devices. I/O Designer was used extensively to manage the unravelling of these connections. By maintaining consistency between the PCB and Schematic data the team could quickly and easily with confidence perform the necessary pin-swaps to optimize the routing without compromising the FPGA internal design. “
  • CES: “Constraints for the data buss’s and clock’s high-speed and timing were entered and managed using the Constraints Editing System. Constraint templates were created for each buss and clock technology group that included the required topology and rules sets. Once defined these were then applied to all relevant nets greatly reducing the time to enter the data. “
  • XtremePCB: “Due to the aggressive project timescales the design team worked concurrently. Before the schematics were fully complete, layout started on the processor/memory section, with updates for both constraints and schematic changes being forward annotated at appropriate stages of the design. Concurrent design was taken a stage further by the use of XtremePCB. Two layout designers routed the board simultaneously with each designer taking ownership of distinct areas of the board such as DDR3, PCI-X, Ethernet etc. “
  • “The pre-layout planning coupled with the concurrent design process and XtremePCB resulted in the board being completed approximately two weeks earlier than scheduled. “

Judge’s comments:

• “One of the best designs for TH (through hole) boards with HDI density of372 pins/sq inch. Exceptional TH layout with 27% layout efficiency where TH normally gets on 6~12%.”

Alcatel-Lucent – TLA ‘Telecom, Network Controllers, Line Cards’ category winner

The 2010 Technology Leadership Awards competition is just around the corner. To showcase the complexity of last year’s entries I’ve been blogging the details of each of the winning designs. The telecom category routinely produces ‘monster’ designs with large dimensions and high layer / net / component counts. Alcatel-Lucent’s entry – the winner in this category – epitomized those characteristics. Alcatel-Lucent has a history of design excellence – another team within the organization claimed the award for best overall design in 2008.

Design team: Susan Plul, Max Ko

End product use: 32 port 10GHz SFP+ board for data centers

Stats:

Design challenges:

• Design for…signal/power integrity, cost, govt. compliance, manufacturability, reliability, testability, and thermal constraints
• Huge component and connection counts; 22477in. of interconnect (.35miles); 35 power rails
• Routing 0.8mm BGA without HDI
• 1500+ point-to-point no-via diff pairs
• Vias designed for reliability (CAF), manufacturability (via dimensions relative to board thickness), testability (on bottom side), performance (back drilling for SERDES lines)
• Extensive high-speed constraints
• Thermal – Air flow and heat dissipation a major concern;  500W power to dissipate; high currents

Design tools:

• Used the Expedition Enterprise flow
• Heavy design reuse for efficiency and reduced cycle time (71% of components within reuse blocks, making placement & routing efficient; also reused schematic/layout design block across designs across multiple global divisions; ensured consistency from board to board).

Judge’s comments:

• “Serious challenges, serious solution, very well documented. No more to say – this designer really knows their stuff.”

Design images:

TLA 2010 – Showcase Your Designs!

The 2010 annual Technology Leadership Awards competition for PCB designs is cranking up this week. It’s a great opportunity to showcase your latest work and compete against designs from across the electronics industry and around the world.

Find out more about the competition, see who won last year, check my blogs for details on the winners.

GE Fanuc – 2009 PCB TLA military & aerospace category winner

Like all good projects, I started blogging about the winners of the 2009 competition, but never finished. I owe it to the winners to cover them all. This one’s about GE Fanuc – the winner of the Military & Aerospace category.

Design team: Nigel Knighton, Dave Shield, Stuart Connolly, Jim Rose, Zeshan Hussein

End product use: System blade for radar, sonar, signal intelligence & image processing

Stats:

Design challenges:

• Design for…signal/power integrity, cost, manufacturability and reliability
• 3+12+3 HDI stack-up
• 22000+ pins; 4500+ components
• Tight placement that achieved SI & thermal constraints (memory placed back-to-back to achieve DDR2 routing requirements)
• 80% high-speed nets
• Serial I/O signals running at 3.125GHz with a period of 320ps

Design tools:

• Used the Expedition Enterprise flow, along with an interface to SolidWorks for mechanical CAD and FloTherm for thermal analysis.
• All the signal length requirements where entered in the form of delay formulae to ensure compliance with the rules.

Judge’s comments:

• “One serious mother of a circuit board, well designed with an intelligent layer stack-up intelligently used.”

Design images:

CiBOARD – 2009 PCB TLA ‘industrial control’ category winner

This blog is part of a series talking about the 2009 Technology Leadership Awards competition and winners in each category. This time we’re highlighting CiBOARD, who won the award in the ‘Industrial Control, Instrumentation, Security & Medical’ category. CiBOARD is a repeat winner in this category.

Design team: Michael Schwitzer

End product use: Preprocessor and correction-unit for high speed measurement / data acquisition in compact cases (first use:  pixel processing in camera studio equipment).

Stats:

Design challenges:

• Design for…signal and power integrity, and reliability
• 2-18-2 HDI stack-up (~16,000 vias; ~10,000 pins)
• Tight performance constraints (multigigabit diff pairs matched within 0.1mm; impedance controlled routing). Data rates of 50-60Gbps across signals.
• 1700+ pin FPGA with DDR, LVDS, SERDES interfaces
• Regional area rules under 0.5mm pitch uBGA
• PowerPC processor at 40gbps
• Terminating resistors placed directly under the FPGA for optimal timing and lower power dissipation
• Small placement area
• Power distribution issues – high currents required for the FPGA core (about 10Amp)
• Coordinated with three target manufacturers

Design tools:

• PADS & Expedition Enterprise flows (PADS for placement, Expedition for routing)
• HyperLynx SI for simulations
• “The first simulations showed the way for effective address-routing…the result was First Time Right.”

Judge’s comments:

• “Unquestionably a complex board, and a credit to the designer. Good use of the tools, and good use of the layers.”

Design images:

Panasonic – 2009 PCB TLA consumer electronics category winner

This blog is part of a series talking about the 2009 Technology Leadership Awards competition and winners in each category. This time we’re highlighting Panasonic, who won the award in the ‘Consumer Electronics & Handheld’ category.

Design team: Takayuki Hinokidani, Shuhei Osako

End product use: Blue-ray and hard disk recorder main digital board

Stats:

Design challenges:

• Design for…signal integrity and cost.
• Most complex component: 857 pin BGA with 1mm pin pitch.
• Used DDR2-800MHz memory with matched length tolerances of 0.3mm-1mm (including package length).
• Didn’t use HDI due to cost constraints.
• Had to minimize area of DDR memory from previous design – gained placement area in the process. Achieved a 21% reduction by eliminating extra passives and miniaturization of one of the components.

Design tools:

• Expedition Enterprise flow, including HyperLynx GHz
• Used HyperLynx to confirm improved signals (length, clearance, termination, impedance) met timing requirements.

Judge’s comments:

• “Good job of routing components both sides. Serious challenges in complexity. Did well to fit into six layers & components on both sides without HDI.”

Design images:

Results of PCB Design Survey

We recently sent a survey on PCB layout to a set of customers. The results identify trends in the areas of: layout design time; collaboration; advanced manufacturing technology adoption; and IP management.

Layout design time

This first area was intended to explore where time is spent during layout and where major bottlenecks exist.

• Time spent on layout activities: In the chart below you can see traditionally high percentages for placement and routing. Constraints and plane design are more recent time sinks – the presumption is that this is due to the increasing volume and complexity of high-speed constraints, and the growing challenge of power integrity. An assumption could be made that the tasks that now consume less time (e.g. documentation & mfg outputs) are a result of increasing automation in these areas.

• On average…
  • It takes 4.5 weeks to layout a board (21% took more than 9 weeks)
  • Designs have 3 to 5 ECOs after the initial layout is complete (33% experienced more than 6 ECOs)
  • 35% of total design time is spent in layout (30% said layout consumes more than 50% of the total)
  • 30% of layout time is spent on high-speed constrained nets
  • 15% of layout time is spent breaking out of high-pin-density components
  • 74% of routing is manual (50% said they do >90% manual)
  • 11% of a design is based on re-used data

Collaboration

This section discusses the changing face of collaboration during the design process including most frequent forms of collaboration and their benefits.

• Time consumed by different areas of collaboration: The traditional interchange between engineering and layout topped the list. Multiple designer layout is an emerging challenge. As noted earlier, perhaps ‘design to manufacturing’ consumes less time now due to automation.

• Most commonly used platforms for collaboration: Email (80%); Conference (61%); DXF, IFF, IDF, etc. (43%); Design viewer (34%); Visio (14%). Other methods noted included: MS Sharepoint/Communicator; A Wiki for collaboration of changes; spreadsheets; and Gerbers, pdf, or trackers (common interacting document).

• Common barriers to effective collaboration: Ambiguous communications (50%); Lack of shared knowledge (43%); Change control (32%); Inefficient data transfer (32%); Geography/time zones/shifts (27%); Validation & signoff (23%); Implementation of recommendations (23%). I’d equate the top two to two people speaking to each other in different languages – they want to communicate, but don’t have a common platform through which they can understand each other.

• Benefits of effective collaboration: It’s no surprise that ‘Reduced design time’ was at the top of the list given the time crunch most teams are under. Of course, since collaboration with others can often be time-consuming in itself, it puts added pressure on the process to streamline the method in which people work together.

Advanced manufacturing technology adoption

Industry technologists have been talking about the advent of ‘advanced’ PCB manufacturing technologies for a long time, yet adoption of these technologies doesn’t seem to match their projections. This section looks at barriers to deployment, as well as reasons why some new technologies are being adopted.

• Things that drive more complexity into the design process: Design density (#pins, pin density, connections, spacing, board size) (93%); Increasing constraints, performance (86%); Use of advanced mfg technologies (HDI, flex, embedded passives, COB) (56%); Complexity is the same, just have less time (16%); Distributed design teams (14%); Other areas included: DFA and DFM; mixed signal design; and increased RF design.

• Advanced PCB manufacturing technologies utilized in designs: HDI/microvias (75%); Chip on board (34%); Embedded passives (23%); Package-on-package (18%); Embedded actives (7%); Cavities (16%); Other areas included: SoC; OSP finishing; flex; back drilling. One also noted that they tried to find innovative ways to avoid HDI – given the cost of advanced technology deployment, sometimes the leaders are the ones getting designs done without incurring the time and cost of a new technology.

• Biggest barriers to incorporation of advanced PCB manufacturing technologies: Cost of implementation (57%); Insufficient knowledge (55%); Lack of expertise amongst fabricators (48%); Insufficient tools/solutions (36%); Benefits of new technology unknown (18%). Others included: need to minimize risk; need to maintain higher yield (higher clearances); “K.I.S.S. methodology works best”; lack of collaboration between design tools and fabricator; and reliability concerns.

• Benefits of incorporating advanced PCB manufacturing technologies:

IP management

This last section reviews forms of intellectual property (IP) management, with a focus on design reuse.

• Frequency that design reuse is incorporated into the design process:

• Main drivers of reuse: Reduce design time/costs (95%); Capturing organizational knowledge / best practices (55%); Reducing product costs (45%); Higher product quality (34%); Reduction in component diversity (27%). Others included: Leveraging proven ideas and design consistency (I’d put these under ‘best practices’); and ability to scale designs quickly.

• Barriers to effective data reuse: Poor upfront capture of reuse blocks (59%); Difficulty finding the blocks you need (39%); Difficulty storing reusable data in a central repository (36%); Can’t understand the intent of the reuse block (14%); Not motivated to reuse other’s work (9%). Others included: Tool limitations; Schematic only fits partially, layout fits less; Reuse isn’t beneficial within service companies; Technology moves too fast to re-use older designs; Multiple layer stack-ups to manage; Several customers to support; Takes a lot of time to update complex reuse blocks.

• Most valuable forms of design IP: Component libraries (43%); Design data (27%); Design processes (14%); Reuse block libraries (7%); Constraint sets (5%); Flow customization (2%).

• Existence of a centralized PCB parts library in the company: Yes (84%); No (16%).

My thanks to those who participated in the study. We’ll be exploring some of these challenges (and potential solutions) in a webinar series.

Kontron – 2009 PCB TLA computer category winner

This blog is part of a series talking about the 2009 Technology Leadership Awards competition and winners in each category. This time we’re highlighting Kontron Canada, who won the award in the ‘Computers, Blade & Servers, Memory Systems’ category.

End product use: Embedded ATX dual Xeon server motherboard

Stats:

Design challenges:

• Design for…signal & power integrity, cost, manufacturability, reliability and government compliance.
  • DfSI:  Stub length, pair matching, min and max length, length matching, group length matching, length reference, group length reference, maximum via, impedance control and fiber weave effect, trace xtalk, group xtalk.
  • DfPI: Thermal sensor, thermal flow, voltage drop, current flow, voltage sense, copper weight.
  • DfC: Find Asian parts and NA parts for prototype and Asian high volume capacity.  The low layer count and inexpensive RoHS and LF compliant FR4 material.  Using off-the-shelf parts.  5 year parts availability.
  • DfM : Asian high volume ready, part to part, part to board and assembly equipment feature, panel ready, sticker location, connector location for integration ease.
  • DfT: ~3900 test pads (100% of none JTAG pins, and more) giving 100% test coverage.
  • DfR: Shock & vibration – HALT test and 50G shock test.
  • DfG: RoHS, WEEE, UL, CE, FCC, CSA, and more.
  • Other constraints: Rev0 100% functional, concurrent engineering with layout stage for design maturity, design layout around-the-clock with Asian subcontractor to realize short schedule and low cost resource usage.

• The most complex component from a layout perspective was the Intel Nehalem CPU of the latest Xeon family – mounted onto a 1366 pin socket.  It required consideration of tolerances for a heat sink mechanical attachment, and part proximities for the zero-in-force door. High current requirements (total 300A for the dual CPU) required close decoupling and made it a hot spot.
• Worst case rise time of 32ps and 6.4gbps data rates.
• 17,000+ connections on 4 layers – high density routing without microvias

Design tools:

• Expedition Enterprise flow
• Copy/Move Circuit to enable rotated any-angle fiberweave routing
• “Use of rule areas for the device breakouts does enable to have typical rule and tighter rules inside BGA areas.”
• XtremePCB: “improve development schedule and team management”

Judge’s comments:

• “Exceptionally good use of routing room. Odd angle routing very impressive. Fitting into eight layers quite a challenge, successfully accomplished. Well documented.”
• “Best In Category. The challenges of bringing this design to completion on 4 routing layer, with all of the class rules and constraint rules impressed me.”

Design images:

Tellabs – 2009 PCB TLA overall winner

The 2009 Technology Leadership Awards competition featured stiff competition in all categories. In addition to winners in each industry category, an overall winner was also selected. Tellabs Operations won this award with a ‘telecom, network controllers & line cards’ category entry.

Overall winner: Tellabs Operations

Design team: Stephen Mihal, Steven Everly

End product use: Sonet switch module for optical transport product

Stats:

Design challenges:

• Design for…signal/power integrity, cost, manufacturability and reliability.
• The most complex component was a 1669 FBGA with numerous tight constraints to DDR2 banks and 6.25 Gbps signals to a backplane connector.
• Tight timing margins required extensive constraint formulas – with tons of diff pairs, ground shielding and curved traces (e.g. diff pair tolerances down to 0.001”). Over 90% of the nets had high-speed constraints.
• Signal, power and thermal constraints evolved as the layout was underway, requiring updates.
• On-board primary 48 volt and filtered secondary power required trace rules for current carrying capacity and lightning protection. The protected secondary power fed the boards 12 main power rails, this in turn fed 120 filtered powers within the rest of the design.
• Had tight time constraint, so used 2 layout designers simultaneously – also worked concurrently with engineering.
• Thermal simulation determined the need for 5 BGAs to mount spring clip heat sinks and 1 BGA requiring a heat pipe to cool the device.
• The 6.25 Gig routes required the through board vias to be back-drilled.
• Manual pin swapping was required to reduce trace crossing and improve signal integrity on all 6.25 gig traces.
• 300 pin fiber optic tuner and fiber cables required close interaction with mechanical and manufacturing groups to ensure cable radiuses were not violated and that a heat sink fiber optical cable carrier was viable.

Design tools:

• Expedition Enterprise flow
  (DxDesigner, CES, Expedition PCB, XtremePCB, FabLink XE, HyperLynx)
• “The use of XtremePCB, the use of cluster attributes to group components quickly to finalize the design floorplan, and the ability to cross probe between the design and schematic or CES database were crucial to our success. “
• “Utilized XtremePCB to double-team during the entire layout design phase – floorplan, placement, fan-out, defining power layers, routing and trace tuning.”
• “HyperLynx simulation was run to model design considerations. “

Judge’s comments:

“Another design in the hands of a very capable team. Excellent use of the layer stack.”

Design images:

PCB design trends show increasing complexity

The Mentor Graphics annual Technology Leadership Awards competition provides a snapshot of PCB design trends across all electronics industries. I’ve included a table below based on TLA entry averages.

As expected, there’s a general theme of increased design density over the years. This can be seen in the reduction of trace widths/clearances and average pins/in2. The board size and layer count have stayed relatively the same, except for consumer and industrial applications – but everyone’s having to put a ton more functionality in the same form factor. For layer stack-ups there used to be a clear distinction between power/ground and signal layers. Now, to support an increase in voltage and current requirements within a fixed layer count, planes are often are often combined with other planes and signals on a layer. This creates a host of challenges including current delivery, voltage drop, impedance control, current return paths, and noise management.

The transition from many mid-sized components to a few actives with tons of supporting passives is driven by continuing system integration on chip. There is a corresponding increase in nets and connections (more functionality per chip), and a decrease in average leads/part (high percentage of 2-pin resistors and capacitors).

Telecom/networking cards continue to set the mark for size (board area, layers) and number of components/nets/connections/vias. Consumer electronics are on the other end of the board size scale, while managing the highest design densities. The percentage of high-speed-constrained nets is up across all industries, but computer designs maintain the lead.

Design 15 years ago

• Clocks were around 66MHz, and signals had nanosecond rise times – quite pedestrian by today’s picosecond standards.
• Placement was dual-sided, with SMD emerging as the standard. Vias were mostly through-hole.

Design 10 years ago

• Processors were around 750MHz, clocks at 100MHz, and rise times dipped under a nanosecond.
• BGAs were starting to gain popularity, but only had 100-200 pins.
• Microvias were emerging as a solution to the design density challenge.
• ‘Small’ cell phone boards were 5” tall.
• Many nets had basic impedance control/constraints as design for performance became more common.

2009 Technology Leadership Awards – The results are in!

We recently finished our annual Technology Leadership Awards (TLA) contest, and our esteemed panel of PCB industry experts picked another set of incredible designs. Over the next few blogs I’ll tell you about the winners and what made them unique – but if you can’t wait for the results, you can get the basic information from the press release or the TLA home page.

I’d like to start by going over some statistics from this year’s contest, just to give a PCB geek’s perspective on the complexity of designs today.

• Biggest board: 19.3”x14.5” (490x368mm)
• Smallest board: 0.49”x0.42” (12.5×10.6mm)
• Most layers: 32
• Average trace/space: 4/4th (100x100um)
• Most vias: 73847
• Most nets: 13178
• Largest % high-speed nets: 93%
• Most connections: 55982
• Most components: 22236
• Most FPGAs: 48

Managing numbers like that (e.g. for connections or components) is never an easy problem, regardless of how big the board is or how many layers it has. What’s significant is that the board size (X, Y and layers) is shrinking as the functionality increases. Usage of HDI is increasing, but a number of designs are being built with HDI geometries (e.g. 3-4th), but without HDI technology. That inevitably means a major productivity hit for the poor designers who have to route with that density. The answer in part is design re-use – very few designs are started from scratch – many leverage blocks of design data for chip sets or functions from previous designs.

Leveraging advanced technologies

We asked entrants to specify which advanced technologies they utilized for their designs. The results were fairly predictable, although I’d expect bigger numbers for RF and flex given industry trends. HDI usage is steadily increasing – but at the same time note that while a number of people are considering it due to tight densities, they are still avoiding it due to manufacturing or cost concerns.

Advanced technology usage:

• HDI: 44%
• RF/microwave: 17%
• Flip chip: 13%
• Flex/rigid flex: 7%
• Chip on board: 6%
• Buried capacitance: 6%
• Embedded passives: 4%

Design constraints

We also asked entrants to specify the constraints they had to consider during the design process. Not surprisingly, signal integrity and manufacturability ranked very high on people’s lists. This effectively represents the challenges layout designers face – managing  trade-offs between constraints from the front-end (engineering), and the back-end (manufacturing). As an illustration of best-in-class processes, almost all of the TLA winners designed for signal integrity and manufacturability.

Design for…

• Signal integrity: 89%
• Manufacturability: 89%
• Reliability: 69%
• Power integrity: 63%
• Cost: 59%
• Government compliance: 13%

Of interest was the rather large percentage of people designing for power integrity – this is definitely a rapidly rising challenge. There is also a strong correlation between SI and PI – almost all designs that were PI-constrained were also SI-constrained.

There was some variance in constraints by industry, but not as much as in the past. Industries are seeing common drivers (e.g. long gone are the days when mil/aero designers didn’t have to care about time & cost). In addition, the reuse of computer chip sets/functions in different markets has propagated the high-speed constraint sets, helping to make design for SI almost ubiquitous across all markets.

I’ve included a few images of SI-constrained boards that were submitted.

In the next installment I’ll discuss a few trends illustrated by TLA entries over the last 15 years.